Wanted: Standard Design Constraints


Lately, there has been increasing discussion in the industry about the need for a set of standards that specifically support an interoperable description of intent for analog and custom design, a.k.a. “analog design intent” standards. The driving need for such standardization is to enable far greater exchange of analog intent, with greater formalism and clarity, to greatly improve time-to-... » read more

Is There Light At The End Of Moore’s Tunnel?


Last month’s article, “Is There Light At The End Of Moore’s Tunnel,” examined the state of the industry in terms of integrating photonics components onto silicon. It concentrated on the piece that has been the hardest to achieve – the laser. However, as realizing that integration goal has become closer to reality, it has also waned in terms of the number of people who believe it is th... » read more

The Week In Review: System-Level Design


Synopsys won a deal with Germany’s Hyperstone, which will use Synopsys verification tools for SoCs in industrial, automotive and medical applications. As SoCs used in industrial and “safety-critical” markets grow in complexity and move to more advanced process nodes, more advanced tools also are necessary. Si2 uncorked a new release of its OpenAccess scripting interface—oaScript Exte... » read more

Is There Light At The End Of Moore’s Tunnel


Electrons are slow, clumsy and quite easily distracted. They’re slow because it now takes a signal longer to cross a chip than the period of the clock signal. They often don’t travel in straight lines as they collide with other atoms. And electromagnetic interference between adjacent signals can mess with the information they are transferring. On the other hand, light has none of these p... » read more

Experts At The Table: What’s Next?


Semiconductor Engineering sat down with Jim Hogan, long-time industry venture capitalist; Simon Bloch, senior director at Samsung Electronics; Sumit DasGupta, formerly Si2 senior vice president of engineering; and Mike Gianfagna, vice president of marketing at eSilicon (VP of corporate marketing at Atrenta when this roundtable was held). What follows are excerpts of that discussion. SE: What... » read more

The Week In Review: System-Level Design


Si2’s OpenPDK rolled out its Open Process Specification 1.1, including elements necessary to automatically create a process design kit using any EDA vendor’s design flow. The standard uses formal grammar based on the XML Schema Definition. ARM won a deal with Rockchip, which is extending its license to a number of ARM processors as well as its GPU and interconnect technology. This marks ... » read more

The Problem With EDA Standards


In the EDA industry, does standard mean the same as it does in most industries? The Free Dictionary defines it as: Something, such as a practice or a product, that is widely recognized or employed, especially because of its excellence. In the EDA industry, a standards body is the place where EDA companies and customers come together to try and bring about convergence, often in a new or emerging... » read more

Blog Review: Oct. 30


Mentor’s Nazita Saye has stumbled on a phone that you can build yourself from various components. When something breaks, you simply change out what’s broken. Wasn’t that the concept behind the original Volkswagen Beetle? Cadence’s Brian Fuller launches into the discussion about 16nm headaches, including finFET parasitics, pin access and wire resistance. Looks like the transition to f... » read more

Lessons From The Big Apple


Apple this week announced some big changes in their product lineup. Having already released their MacBook Air with the power-sipping Intel Haswell processor, Apple has made further strides with an operating system upgrade that extends battery life by yet another 10% to 15%. For those deep into technology, you may already know that low-power design capability wasn’t created overnight. It h... » read more

A Tale Of Two Standards


By Ed Sperling It could well be one of the strangest developments in standards history. Two competing standards for power formats were rolled out in the middle of the last decade and aside from a few cries of foul they fell below the radar screen of most chip designers and architects for a half-dozen years. Fast forward to the present and the Common Power Format (CPF) and Unified Power Form... » read more

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