tag: Si2

Considerations For Choosing The Right Low-Power Tools
By Ed Sperling - 15 Oct, 2009 - Comments: 0

By Cheryl Ajluni Regardless of what you are designing these days, one fact holds true: Your design is only as good as the design tools you use. Gone are the days when a design could be done on the back of napkin. Today, engineers require a complex ecosystem of interworking tools to guide them through the complex design flow. This is especially true when it comes to low-power design, as i... » read more

Experts At The Table: Evolving Standards
By Ed Sperling - 24 Sep, 2009 - Comments: 0

System-Level Design sat down with Keith Barkley, senior engineer in IBM’s systems and technology group; Steven Schulz, president and CEO of Silicon Integration Initiative (Si2); Yatin Trivedi, director of standards and interoperability programs at Synopsys; Ian Mackintosh, chairman of the OCP International Partnership (OCP-IP), and Michael Meredith, vice president of technical marketing at ... » read more

Experts At The Table: Evolving Standards
By Ed Sperling - 04 Sep, 2009 - Comments: 0

System-Level Design sat down with Keith Barkley, senior engineer in IBM’s systems and technology group; Steven Schulz, president and CEO of Silicon Integration Initiative (Si2); Yatin Trivedi, director of standards and interoperability programs at Synopsys; Ian Mackintosh, chairman of the OCP International Partnership (OCPIP), and Michael Meredith, vice president of technical marketing at For... » read more

Experts At The Table: Evolving Standards
By Ed Sperling - 27 Aug, 2009 - Comments: 0

System-Level Design sat down with Keith Barkley, senior engineer in IBM’s systems and technology group; Steven Schulz, president and CEO of Silicon Integration Initiative (Si2); Yatin Trivedi, director of standards and interoperability programs at Synopsys; Ian Mackintosh, chairman of the OCP International Partnership (OCPIP), and Michael Meredith, vice president of technical marketing at For... » read more

Verifying Low-Power IP And Designs
By Ed Sperling - 13 Mar, 2009 - Comments: 0

By Ed Sperling Verification has always been the time-consuming part of designs. Even at 120nm and above, where power wasn’t much of an issue, verification accounted for an estimated 70 percent of the non-recurring engineering expense in a chip. Since then, the tools to automate design have become more effective, but the complexity of designs has grown by leaps and bounds beyond those tools.... » read more

Low-Power Standards War
By Ann Mutschler - 13 Mar, 2009 - Comments: 0

To the uninitiated, establishing a technology standard may seem straightforward. In reality, the process is mired with technical and political issues as evidenced by the ongoing battle for a de facto low-power design standard between the Unified Power Format (UPF) and the Common Power Format (CPF).   Currently, UPF is with the IEEE for final ratification as P1801, set for vote this month, ... » read more

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