tag: Siemens EDA

Chip Aging Opens Up New Attack Vectors
By Adam Kovac - 03 Apr, 2025 - Comments: 0

The longer a piece of silicon is out in the field the more prone it becomes to a cyberattack, raising questions about the optimal longevity of circuits and the impact of extending their lifetimes. This is particularly challenging for safety- and mission-critical applications, where the cost of development can run as high as $100 million for some of the most complex designs. Chipmakers want t... » read more

HyperLynx
By Siemens EDA - 03 Apr, 2025 - Comments: 0

You gain the full power of HyperLynx when it is fully integrated as part of the Xpedition PCB design flow. Yet, it also interfaces with most PCB layout tools, allowing any engineer to quickly import and set up their PCB designs for analysis, regardless of their existing toolset. And because its progressive verification methodology analyzes a design in stages, HyperLynx locates issues earlier an... » read more

Blog Review: Apr. 2
By Jesse Allen - 02 Apr, 2025 - Comments: 0

Synopsys’ Meenakshy Ramachandran explores how DisplayPort Automotive Extensions help meet functional safety and security standards for the increasingly higher-resolution and more immersive in-vehicle displays in connected, autonomous, shared, and electric vehicles. Siemens’ Gabriella Leone and Michael Munsey discuss the need for a collaborative semiconductor business platform and how to ... » read more

How AI And Connected Workflows Will Close The Verification Bottleneck
By Harry Foster - 27 Mar, 2025 - Comments: 0

For decades, verification has been the unsung hero of chip development—quietly catching bugs before they reach silicon. But as semiconductor complexity has skyrocketed, verification has turned into the bottleneck of development cycles. This challenge has a name: Verification Productivity Gap 2.0. Back in the early 2000s, the Verification Productivity Gap 1.0 emerged when design complexi... » read more

Challenges In Managing Chiplet Resources
By Ann Mutschler - 27 Mar, 2025 - Comments: 0

Managing chiplet resources is emerging as a significant and multi-faceted challenge as chiplets expand beyond the proprietary designs of large chipmakers and interact with other elements in a package or system. Poor resource management in chiplets adds an entirely new dimension to the usual power, performance, and area tradeoffs. It can lead to performance bottlenecks, because as chiplets co... » read more

First-Time Silicon Success Plummets
By Ed Sperling - 27 Mar, 2025 - Comments: 0

First-time silicon success is falling sharply due to rising complexity, the need for more iterations as chipmakers shift from monolithic chips to multi-die assemblies, and an increasing amount of customization that makes design and verification more time-consuming. Details from a new functional verification survey[1] highlight the growing difficulty of developing advanced chips that are both... » read more

A Novel Approach For HW/SW Co-Verification
By Siemens EDA - 27 Mar, 2025 - Comments: 0

The complexity of system on chips (SoCs) continues to grow rapidly. Accordingly, new standards and methodologies are introduced to overcome these verification challenges. The Portable Test and Stimulus Standard (PSS) from Accellera is one of the standard examples used to pursue such challenges. In this paper we will show a methodology to use PSS to orchestrate the process of HW/SW co-verificati... » read more

Digital Twins For Design And Verification Workflows
By Brian Bailey - 27 Mar, 2025 - Comments: 0

Experts At The Table: AI is starting to impact several parts of the EDA design and verification flows, but so far these improvements are isolated to a single tool or small flows provided by a single company. What is required is a digital twin of the development process itself, on which AI can operate. Semiconductor Engineering sat down with a panel of experts, including Johannes Stahl, senior d... » read more

The Evolving Role Of AI In Verification
By Ann Mutschler - 26 Mar, 2025 - Comments: 0

Experts At The Table: The pressure on verification engineers to ensure the functional correctness of devices has increased exponentially as chips have gotten more complex and evolved into SoC, 3D-ICs, multi-die chiplets and beyond. Semiconductor Engineering sat down with a panel of experts, which included Josh Rensch, director of application engineering at Arteris; Matt Graham, senior group dir... » read more

Blog Review: Mar. 26
By Jesse Allen - 26 Mar, 2025 - Comments: 0

Siemens' Bianca Ward argues that sustainability must be considered starting from the design phase to reduce the energy consumption of ICs as well as the production processes used to manufacture them. Synopsys' Adrien Tozzoli looks at how physical optics simulation can be improved by using beam synthesis propagation, a method that decomposes the optical field into a collection of beamlets to ... » read more

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