tag: Siemens EDA

Power Budgets Optimized By Managing Glitch Power
By Adam Kovac - 16 Jan, 2025 - Comments: 0

“Waste not, want not,” says the old adage, and in general, that’s good advice to live by. But in the realm of chip design, wasting power is a fact of physics. Glitch power – power that gets expended due to delays in gates and/or wires – can account for up to 40% of the power budget in advanced applications like data center servers. Even in less high-powered circuits, such as those fou... » read more

Tame IR Drop Like Google
By Jeff Wilson - 16 Jan, 2025 - Comments: 0

In the relentless pursuit of semiconductor performance and efficiency, tech giants like Google are constantly pushing the boundaries of what's possible. As they scale their designs to the cutting-edge 3nm node, power integrity has emerged as a critical challenge that must be overcome. Enter Calibre DesignEnhancer (DE), Siemens' analysis-based solution for enhancing design reliability and man... » read more

What’s The Best Way To Sell An Inference Engine?
By Bryon Moyer - 16 Jan, 2025 - Comments: 0

The burgeoning AI market has seen innumerable startups funded on the strength of their ideas about building faster, lower-power, and/or lower-cost AI inference engines. Part of the go-to-market dynamic has involved deciding whether to offer a chip or IP — with some newcomers pivoting between chip and IP implementations of their ideas. The fact that some companies choose to sell chips while... » read more

How Google And Intel Use Calibre DesignEnhancer To Reduce IR Drop And Improve Reliability
By Siemens EDA - 15 Jan, 2025 - Comments: 0

In the fast-paced world of semiconductor design, achieving both Design Rule Check (DRC) clean layouts and optimal electrical performance is crucial for minimizing design iterations, reducing time-to-market and ensuring product reliability. This paper explores how the Calibre DesignEnhancer (DE) analysis-based, signoff-quality EMIR solution helps design teams meet these challenges by enhancing p... » read more

AI Won’t Replace Subject Matter Experts
By Adam Kovac - 15 Jan, 2025 - Comments: 0

Experts at The Table: The emergence of LLMs and other forms of AI has sent ripples through a number of industries, raising fears that many jobs could be on the chopping block, to be replaced by automation. Whether that’s the case in semiconductors, where machine learning has become an integral part of the design process, remains to be seen. Semiconductor Engineering sat down with a panel of e... » read more

Blog Review: Jan. 15
By Jesse Allen - 15 Jan, 2025 - Comments: 0

Siemens EDA's Stephen V. Chavez argues that the placement of decoupling capacitors on a PCB can make or break a design's power delivery system and provides some best practices and design considerations, such as ensuring even distribution on a board rather than crowding them around chips. Synopsys' Stelios Diamantidis predicts that in 2025, AI agents will begin collaborating with other AI age... » read more

Using Test And Metrology Data For Dynamic Process Control
By Gregory Haley - 14 Jan, 2025 - Comments: 0

Advanced packaging is transforming semiconductor manufacturing into a multi-dimensional challenge, blending 2D front-end wafer fabrication with 2.5D/3D assemblies, high-frequency device characterization, and complex yield optimization strategies. These combinations are essential to improving performance and functionality, but they create some thorny issues for which there are no easy fixes. ... » read more

Screening For Known Good Interposers
By Anne Meixner - 14 Jan, 2025 - Comments: 0

Ensuring the quality of silicon and organic interposers is becoming harder as the number of signals passing through them continues to grow, fueled by more chiplets, higher processing demands, and more layers of devices assembled in a package. Interposers initially were viewed as relatively simple conduits. That perception has changed rather dramatically in recent years with the growing focus... » read more

Streaming Scan Network
By Siemens EDA - 14 Jan, 2025 - Comments: 0

Tessent Streaming Scan Network (SSN) is a system for packetized delivery of scan test patterns. It enables simultaneous testing of any number of cores with few chip-level pins, and reduces test time and test data volume. With SSN, DFT engineers have a true SoC DFT solution without compromises between implementation effort and manufacturing test cost. Challenges with DFT for complex SoCs The... » read more

No-Compromise Packetized Test Improves DFT Efforts
By Peter Orlando - 14 Jan, 2025 - Comments: 0

Design for Test (DFT) managers often must make difficult and sometimes costly trade-offs between test implementation effort and manufacturing test cost. The traditional method for evaluating these trade-offs has been to use hierarchical DFT methods in a divide-and-conquer approach. In hierarchical DFT efforts, all implementation, including pattern generation and verification, is done at the cor... » read more

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