Chip Industry Week in Review

By The SE Staff - 27 Jun, 2025 - Comments: 0

AI featured big at this week's Design Automation Conference (DAC) in San Francisco. Dozens of companies featured AI-related tools (see product section below), as well as significant improvements to existing tools and some entirely new approaches for designing chips. Among the highlights: Siemens unveiled an AI-enhanced toolset for the EDA design flow that enables customers to integrate the... » read more

Mixed Messages Complicate Mixed-Signal

By Brian Bailey - 26 Jun, 2025 - Comments: 0

Several years ago, analog and mixed signal (AMS) content hit a wall. Its contribution to first-time chip failure doubled, and there is no evidence that anything has improved dramatically since then. Some see that the problem is likely to get worse due to issues associated with advanced nodes, while others see hope for improvement coming from AI or chiplets. Fig. 1: Cause of ASIC respins. S... » read more

Distributing Intelligence Inside Multi-Die Assemblies

By Ed Sperling - 26 Jun, 2025 - Comments: 0

The shift from SoCs to multi-die assemblies requires more and smarter controllers to be distributed throughout a package in order to ensure optimal performance, signal integrity, and no downtime. In planar SoCs, many of these kinds of functions are often managed by a single CPU or MCU. But as logic increasingly is decomposed into chiplets, connected to each other and memories by TSVs, hybrid... » read more

Security Vulnerabilities Difficult To Detect In Verification Flow

By Ann Mutschler - 26 Jun, 2025 - Comments: 0

As designs grow in complexity and size, the landscape for potential hackers to infiltrate a chip at any point in either the design or verification flow increases commensurately. Long considered to be a “safe” aspect of the design process, verification now must be a focus of chip developers from a security perspective. This also means the concept of trust has never been higher, and the tr... » read more

Blog Review: June 25

By Jesse Allen - 25 Jun, 2025 - Comments: 0

Siemens’ John McMillan provides a detailed overview of 3D-IC technology and heterogeneous integration, from the market trends driving its adoption to the design, verification, and manufacturing challenges involved. Synopsys’ Gunnar Braun and Stewart Williams check out how cloud-based development practices and virtual prototypes can enable earlier and more efficient testing and validation... » read more

EDA’s Top Execs Map Out An AI-Driven Future

By Ed Sperling - 23 Jun, 2025 - Comments: 0

Artificial intelligence is permeating the entire semiconductor ecosystem, forcing fundamental changes in AI chips, the design tools used to create them, and the methodologies used to ensure they will work reliably. This is a global race that will redefine nearly every domain over the next decade. In presentations and interviews over the past several months, top EDA executives converged on th... » read more

Are Larger Reticle Sizes On The Horizon?

By Katherine Derbyshire - 19 Jun, 2025 - Comments: 0

Making high-NA EUV lithography work will take a manufacturing-worthy approach to stitching together circuits or a wholesale change to larger masks. Circuit stitching between the exposure fields is challenging the design, yield and manufacturability of the high-NA (0.55) EUV transition. The alternative is a radical change from 6x6-inch to 6x11-inch masks that would eliminate stitching, but it... » read more

Can You Build A Known-Good Multi-Die System?

By Ed Sperling - 18 Jun, 2025 - Comments: 0

Semiconductor Engineering sat down to discuss the challenges of designing and testing multi-die systems, including how to ensure they will work as expected, with Bill Mullen, Ansys fellow; John Ferguson, senior director of product management at Siemens EDA; Chris Mueth, senior director of new markets and strategic initiatives at Keysight; Albert Zeng, senior engineering group director at Cadenc... » read more

Blog Review: June 18

By Jesse Allen - 18 Jun, 2025 - Comments: 0

Synopsys’ John Koeter and other industry experts discuss whether high-bandwidth memory should follow established standards for broad compatibility and scalability or be customized to address specific use case requirements and time-to-market targets. In a podcast, Siemens’ Conor Peick, Dale Tutt, and Mike Ellow chat about how progress in 3D-IC development, thermal management, and the indu... » read more

A Guide To SDC-Based Timing Intent Verification With Questa One

By Siemens EDA - 16 Jun, 2025 - Comments: 0

As semiconductor designs continue to grow in complexity and timing margins become increasingly constrained, achieving predictable timing closure has evolved from a best practice into a critical requirement for first-pass silicon success. At the heart of this process lies the timing constraint file, i.e., the SDC (Synopsys Design Constraints), which defines the intended timing behavior of the de... » read more

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