tag: Siemens EDA

Why Shift Left?
By Michael White - 24 Aug, 2023 - Comments: 0

As every integrated circuit (IC) design company knows, the faster a design can progress from implementation to signoff verification, the better the chances are of meeting tapeout schedules. Meeting tapeout schedules improves a company’s chances of reaching their market targets. But as companies create larger and more complex ICs and move to advanced process nodes, the challenge of achieving t... » read more

Preparing For Commercial Chiplets
By Ed Sperling - 24 Aug, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the path to commercialization of chiplets with Saif Alam, vice president of engineering at Movellus; Tony Mastroianni, advanced packaging solutions director at Siemens Digital Industries Software; Mark Kuemerle, vice president of technology at Marvell; and Craig Bishop, CTO at Deca Technologies. What follows are excerpts of tha... » read more

The Four Foundational Pillars Of Calibre Shift Left Solutions For IC Design And Implementation Flows
By Siemens EDA - 23 Aug, 2023 - Comments: 0

As the semiconductor industry approaches a new era of digital transformation, design companies everywhere are turning to shift left strategies to address challenges that reduce design cycles while maximizing productivity, optimizing resource efficiency, ensuring design quality, and accelerating time to market. To overcome these challenges in IC design, Calibre shift left technologies include to... » read more

Blog Review: Aug. 23
By Jesse Allen - 23 Aug, 2023 - Comments: 0

Siemens' Stephen Chavez discusses best practices when it comes to thermal analysis for PCB design, including component placement and close collaboration between mechanical and electrical engineering disciplines. Synopsys' Gary Ruggles, Richard Solomon, and Varun Agrawal introduce the Compute Express Link (CXL) specification and how it could help improve latency through computational offloadi... » read more

Week In Review: Design, Low Power
By Susan Rambo - 18 Aug, 2023 - Comments: 0

Synopsys’ board of directors appointed Sassine Ghazi as president and chief executive officer effective on Jan. 1, 2024. Ghazi, who is currently the COO, will succeed Aart de Geus, co-founder, chair, and CEO of Synopsys, who will then become the executive chair of board of directors. IBM Research introduced  an energy-efficient mixed-signal analog AI chip for DNN inferencing and demonstra... » read more

Tradeoffs Between On-Premise And On-Cloud Design
By Ann Mutschler - 16 Aug, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down discuss how and why companies are dividing up work on-premise and in the cloud, and what to watch out for, with Philip Steinke, fellow, CAD infrastructure and physical design at AMD; Mahesh Turaga, vice president of business development for cloud at Cadence Design Systems; Richard Ho, vice president hardware engineering at Lightmatter; Cr... » read more

Blog Review: Aug. 16
By Jesse Allen - 16 Aug, 2023 - Comments: 0

Synopsys' Johannes Stahl and Tim Kogel suggest that multi-die systems require a new approach at the architecture planning phase and why chip designers can’t ignore physical effects such as layout, power, temperature, or IR-drop. Siemens' Rich Edelman argues for using the waveform window in a GUI rather than $display when debugging UVM. Cadence's Paul Scannell stresses the need for diver... » read more

Processor Tradeoffs For AI Workloads
By Ann Mutschler - 10 Aug, 2023 - Comments: 0

AI is forcing fundamental shifts in chips used in data centers and in the tools used to design them, but it also is creating gaps between the speed at which that technology advances and the demands from customers. These shifts started gradually, but they have accelerated and multiplied over the past year with the rollout of ChatGPT and other large language models. There is suddenly much more... » read more

MRAM Getting More Attention At Smallest Nodes
By Karen Heyman - 10 Aug, 2023 - Comments: 2

Magneto-resistive RAM (MRAM) appears to be gaining traction at the most advanced nodes, in part because of recent improvements in the memory itself and in part because new markets require solutions for which MRAM may be uniquely qualified. There are still plenty of skeptics when it comes to MRAM, and lots of potential competitors. That has limited MRAM to a niche role over the past couple de... » read more

Fast, Accurate, Automated Via Insertion During Design Implementation Requires Foundry Rule Compliance
By Jimmy Tien - 10 Aug, 2023 - Comments: 0

As the scaling of silicon technology proceeds, via resistance is becoming a dominant factor in integrated circuit (IC) yield, performance, and reliability. At advanced nodes, interconnects and via dimensions decrease, while the number of metallization layers increases. To moderate the impact of via resistance on yield and reliability and reduce electromigration (EM) and voltage drop (IR) effect... » read more

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