tag: Siemens EDA

Balancing Power And Heat In Advanced Chip Designs
By Karen Heyman - 10 Nov, 2022 - Comments: 1

Power and heat use to be someone else's problem. That's no longer the case, and the issues are spreading as more designs migrate to more advanced process nodes and different types of advanced packaging. There are a number of reasons for this shift. To begin with, there are shrinking wire diameters, thinner dielectrics, and thinner substrates. The scaling of wires requires more energy to driv... » read more

Complete Reliability Verification For Multiple-Power-Domain Designs
By Siemens EDA - 09 Nov, 2022 - Comments: 0

With increasing design complexity and a heightened focus on reliability at all levels of integrated circuit (IC) design from intellectual property (IP) to full-chip, accurate and full verification coverage of the different reliability concerns within an IC design is essential. Designs containing multiple power domains add more complexity to reliability verification with the need to validate int... » read more

Blog Review: Nov. 9
By Jesse Allen - 09 Nov, 2022 - Comments: 0

Cadence's Claire Ying finds that the latest update to CXL, which introduced memory-centric fabric architectures and expanded capabilities for improving scale and optimizing resource utilization, could change how some of the world’s largest data centers and fastest supercomputers are built. Synopsys' Gervais Fong and Morten Christiansen examine the latest updates in the USB 80Gbps specifica... » read more

Next Steps For Improving Yield
By Laura Peters - 08 Nov, 2022 - Comments: 0

Chipmakers are ramping new tools and methodologies to achieve sufficient yield faster, despite smaller device dimensions, a growing number of systematic defects, immense data volumes, and massive competitive pressure. Whether a 3nm process is ramping, or a 28nm process is being tuned, the focus is on reducing defectivity. The challenge is to rapidly identify indicators that can improve yield... » read more

How To Improve Yield Ramp For New Designs And Technology Nodes
By Jayant D'Souza - 08 Nov, 2022 - Comments: 0

The complicated silicon defect types and defect distribution of new IC manufacturing technologies can result in very low yield for new designs and technology nodes. During technology qualification using test chips, scan chain failures account for most of the chip failures. Diagnosing those scan chain defects is a powerful way to uncover new and systematic defects. The chip maker’s goal is ... » read more

Week In Review: Semiconductor Manufacturing, Test
By Karen Heyman - 04 Nov, 2022 - Comments: 0

Nikkei Asia reports the U.S. is urging allies, including Japan, to restrict exports of advanced semiconductors and related technology to China. The U.S. holds 12% of the global semiconductor market, Japan has a 15% share, while Taiwan and South Korea each have about a 20% share. Some U.S. companies have called for other countries to adopt U.S.-style export curbs, arguing it is unfair for only A... » read more

What You Need To Know About Qualifying Tools For DO-254 Programs
By Jacob Wiltgen - 03 Nov, 2022 - Comments: 0

By Michelle Lange and Tammy Reeve, Patmos Engineering Services, and Jacob Wiltgen, Siemens EDA DO-254, which is required for airborne electronics development, is a design assurance standard. Design assurance requires multiple layers of review and verification within the development process to ensure safe operation of the design being produced. This means when an engineer is doing design work... » read more

How Do You Qualify Tools For DO-254 Programs?
By Siemens EDA - 02 Nov, 2022 - Comments: 0

This paper describes the terminology and requirements related to tool qualification specific to the safety-critical programs governed by DO-254 compliance. It also provides some practical examples of tool qualification processes and strategies for commonly used tools. Qualifying tools for DO-254 While the use of state-of-the art development tools has led to ever increasing design complexity... » read more

Blog Review: Nov. 2
By Jesse Allen - 02 Nov, 2022 - Comments: 0

Siemens EDA's Harry Foster examines how successful FPGA projects are in terms of verification effectiveness, finding that only 16% of all FPGA projects were able to achieve no non-trivial bug escapes into production, worse than IC/ASIC in terms of first silicon success. Synopsys' Jamie Boote and The Chertoff Group's David London break down best practice guidance and directives U.S. governmen... » read more

Chip Design Shifts As Fundamental Laws Run Out Of Steam
By Ann Mutschler - 31 Oct, 2022 - Comments: 12

Dennard scaling is gone, Amdahl's Law is reaching its limit, and Moore's Law is becoming difficult and expensive to follow, particularly as power and performance benefits diminish. And while none of that has reduced opportunities for much faster, lower-power chips, it has significantly shifted the dynamics for their design and manufacturing. Rather than just different process nodes and half ... » read more

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