Debug This! How To Simplify Coverage Analysis And Closure


For years the process of ASIC and FPGA design and verification debug consisted primarily of comprehending the structure and source code of the design with waveforms showing activity over time, based on testbench stimulus. Today, functional verification is exponentially complex with the emergence of new layers of design requirements (beyond basic functionality) that did not exist years ago — f... » read more

Week In Review: Semiconductor Manufacturing, Test


Micron selected Syracuse, New York as the site for its new megafab complex, which is expected to create 9,000 company jobs and 40,000 construction and supply chain jobs. President Biden called it “another win for America.” The chip manufacturing facility will be the nation’s largest, including a 7.2 million square foot complex and 2.4 million square foot of cleanroom. Site preparation wil... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive, mobility Infineon opened a new factory in Cegléd, Hungary, for assembly and test of high-power semiconductor modules for EVs. “The new manufacturing capacities will help Infineon accommodate the growing demand for electromobility applications,” said Infineon’s COO Rutger Wijburg in a press release. Production ramp-up started in February 2022. Infineon also announced it will ... » read more

Testing Chips For Security


Supply chains and manufacturing processes are becoming increasingly diverse, making it much harder to validate the security in complex chips. To make matters worse, it can be challenging to justify the time and expense to do so, and there’s little agreement on the ideal metrics and processes involved. Still, this is particularly important as chip architectures evolve from a single chip dev... » read more

Auto Safety Tech Adds New IC Design Challenges


The role of AI/ML in automobiles is widening as chipmakers incorporate more intelligence into chips used in vehicles, setting the stage for much safer vehicles, fewer accidents, but much more complex electronic systems. While full autonomy is still on the distant horizon, the short-term focus involves making sure drivers are aware of what's going on around them — pedestrians, objects, or o... » read more

Similar But Different — The Tale Of Transient And Permanent Faults


When determining whether an IC is safe from random hardware faults, applying safety metrics such as PMHF, SPFM, and LFM, engineers must analyze both transient and permanent faults. This paper highlights the fundamental differences between permanent and transient faults on digital circuits, and why this distinction is important in the context of the ISO 26262:2018 functional safety standard. ... » read more

IC Architectures Shift As OEMs Narrow Their Focus


Diminishing returns from process scaling, coupled with pervasive connectedness and an exponential increase in data, are driving broad changes in how chips are designed, what they're expected to do, and how quickly they're supposed to do it. In the past, tradeoffs between performance, power, and cost were defined mostly by large OEMs within the confines of an industry-wide scaling roadmap. Ch... » read more

Week In Review: Manufacturing, Test


Highlights from ITC The hot topic at this week’s International Test Conference (ITC) was tackling silent data corruption, with panel discussions, papers, and Google’s Parthasarathy Ranganathan’s keynote address all emphasizing the urgency of the issue. In the past two years Meta, Google, and Microsoft have reported on silent errors, errors not detected at test, which are adversely impact... » read more

Verification Methodologies Evolve, But Slowly


Semiconductor Engineering sat down to discuss digital twins and what is required to develop and verify new chips across a variety of industries, such as automotive and aerospace, with Larry Lapides, vice president of sales for Imperas Software; Mike Thompson, director of engineering for the verification task group at OpenHW; Paul Graykowski, technical marketing manager for Arteris IP; Shantanu ... » read more

Toward Domain-Specific EDA


More companies appear to be creating custom EDA tools, but it is not clear if this trend is accelerating and what it means for the mainstream EDA industry. Whenever there is change, there is opportunity. Change can come from new abstractions, new options for optimization, or new limitations that are imposed on a tool or flow. For example, the slowing of Moore's Law means that sufficient prog... » read more

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