Reliability Concerns Shift Left Into Chip Design

By Ann Mutschler - 22 Dec, 2021 - Comments: 1

Demand for lower defect rates and higher yields is increasing, in part because chips are now being used for safety- and mission-critical applications, and in part because it's a way of offsetting rising design and manufacturing costs. What's changed is the new emphasis on solving these problems in the initial design. In the past, defectivity and yield were considered problems for the fab. Re... » read more

Challenges With Stacking Memory On Logic

By Ed Sperling - 22 Dec, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the changes in design tools and methodologies needed for 3D-ICs, with Sooyong Kim, director and product specialist for 3D-IC at Ansys; Kenneth Larsen, product marketing director at Synopsys; Tony Mastroianni, advanced packaging solutions director at Siemens EDA; and Vinay Patwardhan, product management group director at Cadence... » read more

EDA In The Cloud Is Driving Semiconductor Innovation

By Nebabie Kebebew - 22 Dec, 2021 - Comments: 0

In the past decade, the move towards cloud computing occurred primarily in sectors like finance, retail, and healthcare, with the emergence of leading public cloud vendors such as Amazon Web Services (AWS), Microsoft Azure, Google Cloud Platform, and others accelerating the trend. However, the chip design industry has been slower to adopt cloud computing. In the current highly competitive en... » read more

Taking 2.5D/3DIC Physical Verification To The Next Level

By Siemens EDA - 21 Dec, 2021 - Comments: 0

As package designs evolve, so do verification requirements and challenges. Designers working on multi-die, multi-chiplet stacked configurations in 2.5/3D IC designs can use Calibre 3DSTACK physical verification checks to verify die alignments for proper connectivity and electrical behavior. The Calibre 3DSTACK precheck mode enables design teams to find and correct basic implementation mistakes ... » read more

Blog Review: Dec. 21

By Jesse Allen - 21 Dec, 2021 - Comments: 0

Cadence's Paul McLellan points to Log4J, a logging utility with a new major vulnerability that could affect hundreds of millions of devices, what's being done to address it, and why the underlying problems may be around for decades. Siemens EDA's Ray Salemi continues explaining how to use Python for verification by checking out the Python logging module for pyuvm and how it compares to UVM r... » read more

Blog Review: Dec. 15

By Jesse Allen - 15 Dec, 2021 - Comments: 0

Arm's Hannah Peeler, Joshua Randall, and Zach Lasiuk examine the carbon cost of data centers and introduce a tool that allows users to make informed decisions about the carbon impact of their compute workloads. Synopsys' Kenneth Larsen provides a primer on the fundamentals of quantum computing, the role of photonics in building quantum systems, and the future potential impact on chip design.... » read more

The Return Of DAC In-Person

By Brian Bailey - 15 Dec, 2021 - Comments: 0

Apart from masked faces everywhere, you could be excused for not knowing that there was a pandemic going on. Sure, the numbers were down, the show floor was smaller, and most of the parties didn't happen, but everyone was so happy to be able to bump elbows with their colleagues. Buttons were available for attendees to show the level of comfort they had with various types of greetings, from "... » read more

Revving Up SiC And GaN

By Ann Mutschler - 13 Dec, 2021 - Comments: 0

Silicon carbide (SiC) and gallium nitride (GaN) are becoming more popular for power electronics, particularly in automotive applications, driving down costs as volumes scale up and increasing the demand for better tools to design, verify, and test these wide-bandgap devices. Both SiC and GaN are proving essential in areas such as battery management in electric vehicles. They can handle much ... » read more

Amdahl Limits On AI

By Brian Bailey - 09 Dec, 2021 - Comments: 0

Software and hardware both place limits on how fast an application can run, but finding and eliminating the limitations is becoming more important in this age of multicore heterogeneous processing. The problem is certainly not new. Gene Amdahl (1922-2015) recognized the issue and published a paper about it in 1967. It provided the theoretical speedup for a defined task that could be expected... » read more

Innovations In Sensor Technology

By John Koon - 09 Dec, 2021 - Comments: 0

Sensors are the “eyes” and “ears” of processors, co-processors, and computing modules. They come in all shapes, forms, and functions, and they are being deployed in a rapidly growing number of applications — from edge computing and IoT, to smart cities, smart manufacturing, hospitals, industrial, machine learning, and automotive. Each of these use cases relies on chips to capture d... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?