Why Every Design IP Needs A Complete QA Methodology


Design IP is a key contributor to innovation in the semiconductor industry today. As the complexity and scale of silicon designs increase, so does design and verification time. Design IP enables modularization and re-use of design components, so that designers can leverage already-existing components as a baseline to accelerate design schedules. Therefore, it is not surprising that the usage of... » read more

Strengthening The Global Semi Supply Chain


Within the semiconductor ecosystem, there are a number of dynamics pointing to the need for new ways of partnering in more meaningful ways that bring resiliency to the global semiconductor supply chain. One of these is the move to bespoke silicon, stemming from a shift in the companies that create most SoCs today -- the hyperscalar cloud providers. These market leaders know their workloads so w... » read more

Interactive Symmetry Checking Provides Faster, Easier Symmetry Verification For Analog And Custom IC Designs


Device symmetry ensures accurate, efficient performance of analog and custom IC designs. However, traditional physical verification for symmetry is complex and time-consuming. Calibre interactive symmetry checking runs inside the design environment to simplify and enhance IC symmetry verification. Design teams can use Calibre interactive symmetry checking to quickly and accurately analyze layou... » read more

How Memory Design Optimizes System Performance


Exponential increases in data and demand for improved performance to process that data has spawned a variety of new approaches to processor design and packaging, but it also is driving big changes on the memory side. While the underlying technology still looks very familiar, the real shift is in the way those memories are connected to processing elements and various components within a syste... » read more

How Mature Are Verification Methodologies?


Semiconductor Engineering sat down to discuss differences between hardware and software verification and changes and challenges facing the chip industry, with Larry Lapides, vice president of sales for Imperas Software; Mike Thompson, director of engineering for the verification task group at OpenHW; Paul Graykowski, technical marketing manager for Arteris IP; Shantanu Ganguly, vice president o... » read more

Minimizing EM/IR Impacts On IC Design Reliability And Performance


By Joel Mercier and Karen Chow As technologies and foundry process nodes continue to advance, it gets more difficult to design and verify integrated circuits (ICs). The challenges become even more apparent in 5nm and below nodes, and as the industry moves away from fin field-effect transistor (finFET) and into gate-all-around field-effect transistor (GAAFET) technologies. There are many prob... » read more

Rethinking Machine Learning For Power


The power consumed by machine learning is exploding, and while advances are being made in reducing the power consumed by them, model sizes and training sets are increasing even faster. Even with the introduction of fabrication technology advances, specialized architectures, and the application of optimization techniques, the trend is disturbing. Couple that with the explosion in edge devices... » read more

Designing For Thermal


Heat has emerged as a major concern for semiconductors in every form factor, from digital watches to data centers, and it is becoming more of a problem at advanced nodes and in advanced packages where that heat is especially difficult to dissipate. Temperatures at the base of finFETs and GAA FETs can differ from those at the top of the transistor structures. They also can vary depending on h... » read more

New Data Management Challenges


An explosion in semiconductor design and manufacturing data, and the expanding use of chips in safety-critical and mission-critical applications, is prompting chipmakers to collect and manage that data more effectively in order to improve overall performance and reliability. This collection of data reveals a number of challenges with no simple solutions. Data may be siloed and inconsistent, ... » read more

Interactive Point-To-Point Resistance Simulations


Point to point (P2P) resistance simulations calculate the effective resistance of the layout traces between points on an IC net trace, and let the designer know that there may be too much parasitic resistance from a particular net trace that would affect the reliability or performance of the circuit. However, traditional P2P simulation runs are time-consuming, and often require multiple iterati... » read more

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