Blog Review: Aug. 21


Cadence's Reela Samuel explores the critical role of PCIe 6.0 equalization in maintaining signal integrity and solutions to mitigate verification challenges, such as creating checkers to verify all symbols of TS0, ensuring the correct functioning of scrambling, and monitoring phase and LTSSM state transitions. Siemens' John McMillan introduces an advanced packaging flow for Intel's Embedded ... » read more

Blog Review: Aug. 14


Cadence's Dimitry Pavlovsky highlights two new features in the AMBA CHI protocol Issue G update that enhance security of the Arm architecture: Memory Encryption Contexts, which allows data in each Realm in the memory to be encrypted with a different encryption key, and Device Assignment, which introduces hardware provisions to support fully coherent caches in partially trusted remote coherent d... » read more

Fantastical Creatures


In my day job I work in the High-Level Synthesis group at Siemens EDA, specifically focusing on algorithm acceleration. But on the weekends, sometimes, I take on the role of amateur cryptozoologist. As many of you know, the main Siemens EDA campus sits in the shadow of Mt. Hood and the Cascade Mountain range. This is prime habitat for Sasquatch, also known as “Bigfoot”. This weekend, ar... » read more

Chip Industry Week In Review


Three Fraunhofer Institutes (IIS/EAS, IZM, and ENAS) launched the Chiplet Center of Excellence, a research initiative to support the commercial introduction of chiplet technology. The center initially will focus on automotive electronics, developing workflows and methods for electronics design, demonstrator construction, and the evaluation of reliability. The UCIe Consortium published the Un... » read more

Power Delivery Challenged By Data Center Architectures


Processor and data center architectures are changing in response to the higher voltage needs of servers running AI and large language models (LLMs). At one time, servers drew a few hundred watts for operation. But over the past few decades that has changed drastically due to a massive increase in the amount of data that needs to be processed and user demands to do it more quickly. NVIDIA's G... » read more

Voltage Drop Now Requires Dynamic Analysis


At one time a relatively infrequent occurrence, voltage drop is now a major impediment to reliability at advanced nodes. Decades ago, voltage drop was only an issue for very large and high-speed designs, where there was concern about supply lines delivering full voltage to transistors. As design margins have tightened in modern advanced designs, controlling voltage drop has become a requiremen... » read more

Blog Review: Aug. 7


Synopsys' Jyotika Athavale and Randy Fish investigate the problem of silent data corruption caused by difficult-to-detect hardware defects that cause unnoticed errors in the data being processed and is becoming an increasingly pressing problem as computing scales massively at a rapid pace with the demands of AI. Siemens' Keith Felton suggests adopting physical design reuse circuits to provid... » read more

Focus Shifts To Application-Specific Workloads


Experts At The Table: EDA has undergone numerous workflow changes over time. Different skill sets have come into play over the years, and at times this changed the definition of what it means to design at the system level. To work out what this means for designers today, and how it looks going forward, Semiconductor Engineering sat down with Michal Siwinski, chief marketing officer at Arteris; ... » read more

Ensure Reliability In Automotive ICs By Reducing Thermal Effects


In the relentless pursuit of performance and miniaturization, the semiconductor industry has increasingly turned to 3D integrated circuits (3D-ICs) as a cutting-edge solution. Stacking dies in a 3D assembly offers numerous benefits, including enhanced performance, reduced power consumption, and more efficient use of space. However, this advanced technology also introduces significant thermal di... » read more

Chip Security Now Depends On Widening Supply Chain


Securing chips is becoming more challenging as SoCs are disaggregated into chiplets, creating new vulnerabilities that involve hardware and software, as well as multiple entities, and extending threats across a much broader supply chain. In the past, much of the cyber threat model was confined to either hardware or software, and where multiple vendors were involved, various chips were separa... » read more

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