tag: Siemens EDA

First-Time Silicon Success Plummets
By Ed Sperling - 27 Mar, 2025 - Comments: 0

First-time silicon success is falling sharply due to rising complexity, the need for more iterations as chipmakers shift from monolithic chips to multi-die assemblies, and an increasing amount of customization that makes design and verification more time-consuming. Details from a new functional verification survey[1] highlight the growing difficulty of developing advanced chips that are both... » read more

A Novel Approach For HW/SW Co-Verification
By Siemens EDA - 27 Mar, 2025 - Comments: 0

The complexity of system on chips (SoCs) continues to grow rapidly. Accordingly, new standards and methodologies are introduced to overcome these verification challenges. The Portable Test and Stimulus Standard (PSS) from Accellera is one of the standard examples used to pursue such challenges. In this paper we will show a methodology to use PSS to orchestrate the process of HW/SW co-verificati... » read more

Digital Twins For Design And Verification Workflows
By Brian Bailey - 27 Mar, 2025 - Comments: 0

Experts At The Table: AI is starting to impact several parts of the EDA design and verification flows, but so far these improvements are isolated to a single tool or small flows provided by a single company. What is required is a digital twin of the development process itself, on which AI can operate. Semiconductor Engineering sat down with a panel of experts, including Johannes Stahl, senior d... » read more

The Evolving Role Of AI In Verification
By Ann Mutschler - 26 Mar, 2025 - Comments: 0

Experts At The Table: The pressure on verification engineers to ensure the functional correctness of devices has increased exponentially as chips have gotten more complex and evolved into SoC, 3D-ICs, multi-die chiplets and beyond. Semiconductor Engineering sat down with a panel of experts, which included Josh Rensch, director of application engineering at Arteris; Matt Graham, senior group dir... » read more

Blog Review: Mar. 26
By Jesse Allen - 26 Mar, 2025 - Comments: 0

Siemens' Bianca Ward argues that sustainability must be considered starting from the design phase to reduce the energy consumption of ICs as well as the production processes used to manufacture them. Synopsys' Adrien Tozzoli looks at how physical optics simulation can be improved by using beam synthesis propagation, a method that decomposes the optical field into a collection of beamlets to ... » read more

What Exactly Are Chiplets And Heterogeneous Integration?
By Bryon Moyer - 20 Mar, 2025 - Comments: 1

The terms “chiplet” and “heterogeneous integration” fill news pages, conference papers, and marketing presentations, and for the most part engineers understand what they're reading. But speakers sometimes stumble during a presentation trying to figure out whether a particular die qualifies as a chiplet, and heterogeneous integration comes in different guises for different people. Both t... » read more

Chip Failures: Prevention And Responses Over Time
By Ed Sperling - 19 Mar, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the causes of chip failures, how to respond to them, and how that can change over time, with Steve Pateras, vice president of marketing and business development at Synopsys; Noam Brousard, vice president of solutions engineering at proteanTecs; Harry Foster, chief verification scientist at Siemens EDA; and Jerome Toublanc, hi... » read more

Blog Review: Mar. 19
By Jesse Allen - 19 Mar, 2025 - Comments: 0

Cadence's Neelabh Singh explains the defined port operations of USB4 that are used to bring transmitters burst and receivers of a design under test into compliance mode and to execute tests like bit error tests, error rate tests, clock switch tests, TxFFE equalization tests, and electrical idle tests. Siemens EDA's Stephen V. Chavez examines the use of blind and buried vias in high-density i... » read more

New Data Center Protocols Tackle AI
By Bryon Moyer - 17 Mar, 2025 - Comments: 1

Compute nodes in AI and HPC data centers increasingly need to reach out beyond the chip or package for additional resources to process growing workloads. They may commandeer other nodes in a rack (scale-up) or employ resources in other racks (scale-out). The problem is there currently is no open scale-up protocol. So far this task has been dominated by proprietary protocols, because much of ... » read more

Fulfilling 3D-IC Trade-Off Analyses (And Benefits) With An AI Assist
By Pratyush Kamal - 13 Mar, 2025 - Comments: 0

As we walk around with supercomputers in our pockets and work at desks on even more powerful supercomputers, a lot of processing has moved to the cloud. As a politician described, this can be problematic on a day when there are no clouds in the sky. The world discovered the truth of those words when Crowdstrike struck on July 19, 2024. System designers who spent years balancing power, performan... » read more

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