tag: Siemens EDA

Pressure Builds To Adopt Virtual Prototypes
By Brian Bailey - 26 Sep, 2024 - Comments: 0

Virtual prototypes, often used as a niche tool in the past, are becoming essential for developing complex systems. In fact, systems companies are finding they no longer can function without them. In the semiconductor industry, a virtual prototype is a model for a system at an abstraction level above RTL. But there is no such thing as 'the' virtual prototype. They are constructed for a partic... » read more

Devising Security Solutions For Hardware Threats
By Adam Kovac - 25 Sep, 2024 - Comments: 0

Experts At The Table: Hardware security has evolved considerably in recent years, but getting products to market is a challenge in an environment where threats are always evolving and rarely predictable. That’s especially true given the sheer volume and variety of products being introduced. Semiconductor Engineering sat down with a panel of experts at the Design Automation Conference in San F... » read more

Blog Review: Sept. 25
By Jesse Allen - 25 Sep, 2024 - Comments: 0

Cadence’s Mamta Rana digs into how PCIe 6.1 ECN builds on the FLIT-based architecture introduced in PCIe 6.0, further optimizing flow control mechanisms to handle increased data rates and improved efficiency but making verification of shared credit updates essential. Siemens’ Nicolae Tusinschi provides a primer on formal verification, including what makes it different from simulation, pr... » read more

New Materials Are in High Demand
By Bryon Moyer - 19 Sep, 2024 - Comments: 0

Materials suppliers are responding to the intense pressures to improve power, performance, scaling, and cost issues, which follows a long timeline from synthesis to development and high volume manufacturing in fabs. The advances in machine learning help present a wide field of candidates, which engineers then narrow to potential use. When building standard logic semiconductor chips, the prim... » read more

Blog Review: Sept. 18
By Jesse Allen - 18 Sep, 2024 - Comments: 0

Siemens’ Kyle Fraunfelter explores the similarities between hurricane forecasting and semiconductor manufacturing to argue for the value of integrating real-time wafer fabrication measurements into the digital twin models used to simulate the semiconductor fabrication process. Cadence’s Rohini Kollipara introduces Display Stream Compression (DSC), which can enable higher resolutions and ... » read more

CXL Thriving As Memory Link
By Karen Heyman - 16 Sep, 2024 - Comments: 0

CXL is emerging from a jumble of interconnect standards as a predictable way to connect memory to various processing elements, as well as to share memory resources within a data center. Compute Express Link is built on a PCI Express foundation and supported by nearly all the major chip companies. It is used to link CPUs, GPUs, FPGAs, and other purpose-built accelerators using serial communic... » read more

Elimination Of Functional False Path During RDC Analysis
By Farhad Ahmed - 12 Sep, 2024 - Comments: 0

Reset domain crossing (RDC) issues can occur in sequential designs when the reset of a source register differs from the reset of a destination register, even if the data path is in the same clock domain. This can lead to asynchronous crossing paths and metastability at the destination register. RDC analysis on RTL designs is done to find such metastability issues in a design, which may occur du... » read more

Is PPA Relevant Today?
By Brian Bailey - 12 Sep, 2024 - Comments: 1

The optimization of power, performance, and area (PPA) has been at the core of chip design since the dawn of EDA, but these metrics are becoming less valuable without the context of how and where these chips will be used. Unlike in the past, however, that context now comes from factors outside of hardware development. And while PPA still serves as a useful proxy for many parts of the hardwar... » read more

Higher Density, More Data Create New Bottlenecks In AI Chips
By Adam Kovac - 12 Sep, 2024 - Comments: 0

Data movement is becoming a bigger problem at advanced nodes and in advanced packaging due to denser circuitry, more physical effects that can affect the integrity of signals or the devices themselves, and a significant increase in data from AI and machine learning. Just shrinking features in a design is no longer sufficient, given the scaling mismatch between SRAM-based L1 cache and digital... » read more

On Analysis Of RDC Issues For Identifying Reset Tree Design Bugs And Further Strategies For Noise Reduction
By Siemens EDA - 12 Sep, 2024 - Comments: 0

Reset tree checks should be viewed thoroughly before reset domain crossing analysis. Static verification tools have many checks for reset tree analysis. This paper discusses the usage of non-resettable registers (NRRs) in reset paths. NRRs can cause metastability in the reset paths and hence thorough verification is a must. The paper discusses reduction of false failure reporting noise strategi... » read more

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