tag: Siemens EDA

Software-Defined Radar Is First Leap On SDV Path
By Junko Yoshida - 06 Mar, 2025 - Comments: 0

Software-defined vehicles (SDVs) have had car company marketers in a veritable tizzy for several years, and while they generally agree on the direction, they differ on the speed and route to adoption. For most OEMs, a wholesale change in vehicle architecture, from hood ornament to trunk-latch, is easier said than done. Legacy systems, both hardware and software, are the millstone around OEMs... » read more

Shift Left With Calibre Pattern Matching
By Siemens EDA - 06 Mar, 2025 - Comments: 0

As integrated circuit (IC) designs become increasingly complex, early-stage verification is crucial to ensure productivity and quality in design processes. The "shift left" verification approach, enabled by Siemens’ Calibre nmPlatform, helps IC design teams to identify and resolve critical issues much earlier in the design cycle. As part of the shift left platform, Calibre Pattern Matching... » read more

Wearable Connectivity, AI Enable New Use Cases
By Liz Allan - 06 Mar, 2025 - Comments: 0

The sensing and processing technology used in smart phones, watches, and rings is starting to be being deployed in a wide variety of wearable devices, ranging from those that fill the gap between sports and med tech, to haptic devices to assist the visually impaired and AR/VR glasses. Emerging applications include payment, building, and factory wearables. Most of these devices process signal... » read more

Automakers Grapple With Fundamental Tech Changes
By Ann Mutschler - 06 Mar, 2025 - Comments: 0

Automotive OEMs are wrestling with a stack of changes that affect every part of their business and technology, from threats of tariffs and shifting geopolitical alliances, to new vehicle architectures, tighter market windows, and a fundamental reordering of relationships and priorities between OEMs and their suppliers. There is no consistency to these developments or a best path to solving t... » read more

Verification Experts Vs. Generalists
By Ann Mutschler - 05 Mar, 2025 - Comments: 0

Experts At The Table: As chips and systems become more complicated, more verification tasks get abstracted. So do we need more specialists who are experts in specific tasks, or do we need more generalists who know how to use the tools but don't necessarily have the depth of understanding? Or do we need some way to balance both? Semiconductor Engineering sat down with a panel of experts, includi... » read more

Simplifying HW/SW Co-Verification With PSS Led UVM And C Tests
By Todd Burkholder - 27 Feb, 2025 - Comments: 0

By Todd Burkholder, Wael Abdelaziz Mahmoud, Tom Fitzpatrick, Vishal Baskar, and Mohamed Nafea The complexity of system on chips (SoCs) continues to grow rapidly with the integration of more functionality onto a single chip. As a result, traditional verification methodologies struggle to keep pace with the growing complexities, leading to longer development cycles and increased risk of design... » read more

Improving Verification Methodologies
By Brian Bailey - 27 Feb, 2025 - Comments: 0

Methodology improvements and automation are becoming pivotal for keeping pace with the growing complexity and breadth of the tasks assigned to verification teams, helping to compensate for lagging speed improvements in the tools. The problem with the tools is that many of them still run on single processor cores. Functional simulation, for example, cannot make use of an unlimited number of c... » read more

Multi-Die Design Complicates Data Management
By Adam Kovac - 27 Feb, 2025 - Comments: 0

The continued unbundling of SoCs into multi-die packages is increasing the complexity of those designs and the amount of design data that needs to be managed, stored, sorted, and analyzed. Simulations and test runs are generating increasing amounts of information. That raises questions about which data needs to be saved and for how long. During the design process, engineers now must wrestle ... » read more

A Novel Approach For Hardware-Software Co-Verification
By Siemens EDA - 26 Feb, 2025 - Comments: 0

The complexity of system on chips (SoCs) continues to grow rapidly. Accordingly, new standards and methodologies are introduced to overcome these verification challenges. The Portable Test and Stimulus Standard (PSS) from Accellera is one of the standard examples used to pursue such challenges. In this paper we will show a methodology to use PSS to orchestrate the process of HW/SW co-verificati... » read more

What Scares Chip Engineers About Generative AI
By Adam Kovac - 26 Feb, 2025 - Comments: 0

Experts At The Table: LLMs and other generative AI programs are a long way away from being able to design entire chips on their own from scratch, but the emergence of the tech has still raised some genuine concerns. Semiconductor Engineering sat down with a panel of experts, which included Rod Metcalfe, product management group director at Cadence; Syrus Ziai, vice-president of engineering at E... » read more

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