Why Is PSS So Important?

By Ed Sperling - 25 Feb, 2020 - Comments: 0

Robert Hoogenstryd, product marketing manager at Mentor, a Siemens Business, talks about the new testbench verification language standard, what are the big advantages of using PSS, what kinds of challenges this language solves, and how much time this approach can save. » read more

Wrestling With Variation In Advanced Node Designs

By Ann Mutschler - 19 Feb, 2020 - Comments: 5

Variation is becoming a major headache at advanced nodes, and issues that used to be dealt with in the fab now must be dealt with on the design side, as well. What is fundamentally changing is that margin, which has long been used as a buffer for variation and other manufacturing process-related problems, no longer works in these leading-edge designs for a couple of reasons. First, margin im... » read more

Blog Review: Feb. 19

By Jesse Allen - 19 Feb, 2020 - Comments: 0

Arm's Urmish Thakker takes a look at TinyML, some of the challenges in developing efficient architectures for resource constrained devices, and an explanation of Kronecker product compression. Mentor's Colin Walls considers whether it's better to use single or multiple returns for a function when writing understandable, readable code. Cadence's Paul McLellan shares highlights from a prese... » read more

EDA In The Cloud

By Ed Sperling - 18 Feb, 2020 - Comments: 0

Michael White, director of product marketing for Calibre physical verification at Mentor, a Siemens Business, looks at the growing compute requirements at 7, 5 and 3nm, why the cloud looks increasingly attractive from a security and capacity standpoint, and how the cloud as well as new lithography will affect the cost and complexity of developing new chips. » read more

Week In Review: Design, Low Power

By Ed Sperling - 14 Feb, 2020 - Comments: 0

Processors Arm rolled out a micro neural processing unit that, when combined with its newest microcontroller, can increase machine learning performance by up to 480 times. The company is aiming the MCU and co-processor across a wide swath of applications. Worth noting is that Arm calls its Cortex-M55 an AI-capable processor, rather than a microcontroller, as the lines between the various proce... » read more

Earlier Is Better In Latch-Up Detection

By Flint Yoder - 13 Feb, 2020 - Comments: 1

Physical verification is an essential step in integrated circuit (IC) design verification. Foundries provide design rule manuals that specify the precise physical requirements needed to ensure the design can be correctly manufactured, and the verification team runs the layout through checks based on those rules to ensure compliance. However, ensuring that a design can be manufactured does not g... » read more

Reducing Power At RTL

By Ann Mutschler - 13 Feb, 2020 - Comments: 0

Power management and reduction at the register transfer level is becoming more problematic as more heterogeneous elements are added into advanced designs and more components are dependent on interactions with other components. This has been a growing problem in leading-edge designs for the past couple of process nodes, but similar issues have begun creeping into less-sophisticated designs as... » read more

Brighter Future For Photonics

By Brian Bailey - 13 Feb, 2020 - Comments: 3

Photons increasingly are taking over where electrons are failing in communications, but mixing the two never has been easy. There always have been two potential implementation paths — building each on its own substrate and then stacking them, or building them on a single substrate. The tradeoff between the two solutions is more complex than it may initially appear, and ongoing improvements... » read more

The MCU Dilemma

By Brian Bailey - 13 Feb, 2020 - Comments: 2

The humble microcontroller is getting squeezed on all sides. While most of the semiconductor industry has been able to take advantage of Moore's Law, the MCU market has faltered because flash memory does not scale beyond 40nm. At the same time, new capabilities such as voice activation and richer sensor networks are requiring inference engines to be integrated for some markets. In others, re... » read more

Blog Review: Feb. 12

By Ed Sperling - 12 Feb, 2020 - Comments: 0

Complexity is growing by process node, by end application, and in each design. The latest crop of blogs points to just how many dependencies and uncertainties exist today, and what the entire supply chain is doing about them. Mentor's Shivani Joshi digs into various types of constraints in PCBs. Cadence's Neelabh Singh examines the complexities of verifying a lane adapter state machine in... » read more

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Knowledge Centers
Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

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