tag: signal integrity

Turning Signal Integrity Simulation Inside Out
By Ansys - 08 Mar, 2017 - Comments: 0

So what does it mean to turn signal integrity simulation inside out? Modern simulation has physics-based solvers in the foreground supported by circuit and system simulation rather than the other way around. All electronic design is fundamentally based on Maxwell’s equations, so naturally the most rigorous way to deliver accurate simulation of high-performance systems is to solve those equ... » read more

The Week In Review: Design
By Jesse Allen - 27 Jan, 2017 - Comments: 0

Tools Cadence launched its Sigrity 2017 technology portfolio for PCB power and signal integrity signoff, adding a power topology viewer and editor, library management for power integrity models, and a PCI Express 4.0 compliance kit for checking signal integrity. Memory Spin Transfer Technologies delivered samples of fully functional ST-MRAM (spin transfer magneto-resistive random acces... » read more

7nm Design Success Necessitates A Multi-Physics Approach
By Youngsoo Lee - 12 Jan, 2017 - Comments: 0

Whether you are designing an energy efficient mobile device, or an ADAS platform with stringent reliability requirements, or a high performance enterprise networking system, chips fabricated on advanced technologies such as 7-nanometer (nm) process and 2.5/3D or wafer level packaging can provide several advantages. Designs using these technologies consume less power while delivering higher thro... » read more

Calibre xACT Parasitic Extraction Supports Signal Integrity At Advanced Nodes
By Mentor, a Siemens Business - 21 Apr, 2016 - Comments: 0

At advanced nodes, signal integrity analysis requires precise characterization, which in turn requires an accurate extracted netlist. Models that handle new impacts on parasitic extraction at advanced nodes, including multi-patterning, finFETs, and resistance and capacitance effects, must be used. Learn how the Calibre xACT extraction tool supports these advanced foundry device models and leadi... » read more

System-Aware Full-Chip Power Integrity And Reliability
By Calvin Chew - 12 Nov, 2015 - Comments: 0

At the core of every electronics system is a chip that has to meet multiple conflicting requirements such as increased functionality, best power efficiency, highest reliability, lowest design cost and short design schedule. Meeting these requirements poses a major challenge, especially for systems on chip (SoCs) that are designed using advanced processes. Ensuring that the SoCs meet power an... » read more

New System Requirements Demand a Creatively Choreographed Ecosystem
By Jim Feldhan - 17 Sep, 2015 - Comments: 0

In the past, integrated circuits, packages and boards were all designed independently, and yet in most cases still managed to fit together with very few functional or technical problems. However, recent advances in chip performance have changed this process dramatically. New designs, processes and materials already have been seen in packaging as high-performance semiconductor chips need to c... » read more

Tackling RF Desense Challenges At The Source
By Margaret Schmitt - 14 Aug, 2015 - Comments: 0

Just imagine you are stepping out of the electronics store with your brand new smart phone. You eagerly scroll down your contacts to dial your best friend and proudly tell them the great news, but as soon as they pick up, your reception is gone! What happened? This problem is commonly described as desense, a degradation of the sensitivity of the receiver due to external noise sources. Desens... » read more

Signal Integrity Issues
By Ed Sperling - 04 Feb, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss signal integrity with Rob Aitken, research fellow at [getentity id="22186" comment="ARM"]; PV Srinivas, senior director of engineering for the Place & Route Division of [getentity id="22017" e_name="Mentor Graphics"]; and Bernard Murphy, chief technology officer at [getentity id="22026" e_name="Atrenta"]. What follows are excerpts of that conver... » read more

First Look: 10nm
By Ed Sperling - 29 Jan, 2015 - Comments: 6

As the semiconductor industry begins grappling with mass production at 14/16nm process nodes, work is already underway at 10nm. Tools are qualified, IP is characterized, and the first test chips are being produced. It's still too early for production, of course—perhaps three years too early—but there is enough information being collected to draw at least some impressions about just how toug... » read more

Signal Integrity Issues
By Ed Sperling - 21 Jan, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss signal integrity with Rob Aitken, research fellow at [getentity id="22186" comment="ARM"]; PV Srinivas, senior director of engineering for the Place & Route Division of [getentity id="22017" e_name="Mentor Graphics"]; and Bernard Murphy, chief technology officer at [getentity id="22026" e_name="Atrenta"]. What follows are excerpts of that conver... » read more

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