Rapid Evolution For Verification Plans

By Brian Bailey - 28 Oct, 2019 - Comments: 0

Verification plans are rapidly evolving from mechanisms to track verification progress into multi-faceted coordination vehicles for several teams with disparate goals, using complex resource management spread across multiple abstractions and tools. New system demands from industries such as automotive are forcing tighter integration of those plans with requirements management and product lif... » read more

Using HLS To Improve Algorithms

By Zubair Wadood - 24 Oct, 2019 - Comments: 0

Can an HLS optimization tool outperform expert-level hand-optimizations? A recently published white paper examines how SLX FPGA is used to optimize a secure hash algorithm. T the results are compared to a competition-winning hand-optimized HLS implementation of the same algorithm. This approach provides a nearly 400x speed-up over the unoptimized implementation and even outperforms the hand ... » read more

Using SLX FPGA For Performance Optimization Of SHA-3 For HLS

By Silexica - 23 Oct, 2019 - Comments: 0

Author: Zubair Wadood SLX FPGA facilitates converting your C/C++ project into an FPGA bitstream easier and with higher performance. Leveraging standard HLS (High Level Synthesis) tools from FPGA vendors, SLX FPGA tackles the challenges associated with the HLS design flow. In this paper, the results of an SLX FPGA-optimized implementation of a Secure Hash Algorithm (SHA-3; also known as Kecca... » read more

Focus Shifts To Wasted Power

By Brian Bailey - 10 Oct, 2019 - Comments: 0

Mobile phones made the industry aware of power, but now the focus is shifting to the total energy needed to perform a task. Activity that is unnecessary to perform the intended task is wasted power, and reducing it requires some new methodologies and structural changes within development teams. There is a broadening awareness about power. "The companies doing SoCs for mobile lead the charge ... » read more

Synthesizing Hardware From Software

By Brian Bailey - 22 Aug, 2019 - Comments: 1

The ability to automatically generate optimized hardware from software was one of the primary tenets of system-level design automation that was never fully achieved. The question now is whether that will ever happen, and whether it is just a matter of having the right technology or motivation to make it possible. While high-level synthesis (HLS) did come out of this work and has proven to be... » read more

Chiplets, Faster Interconnects, More Efficiency

By Ed Sperling - 22 Aug, 2019 - Comments: 1

Big chipmakers are turning to architectural improvements such as chiplets, faster throughput both on-chip and off-chip, and concentrating more work per operation or cycle, in order to ramp up processing speeds and efficiency. Taken as a whole, this represents a significant shift in direction for the major chip companies. All of them are wrestling with massive increases in processing demands ... » read more

Facilitating High Level Synthesis from MATLAB generated C C++

By Silexica - 21 Aug, 2019 - Comments: 0

MATLAB is the go-to toolbox for high level algorithm design in many application domains, ranging from signal processing to control systems and data analysis. MATLAB Coder generates executable C/C++ code from MATLAB implementations. However, the performance requirements of these applications often mandate a hardware implementation. SLX FPGA helps transform the auto-generated C/C++ code into a sy... » read more

Hardware-Software Co-Design Reappears

By Brian Bailey - 25 Jul, 2019 - Comments: 1

The core concepts in hardware-software co-design are getting another look, nearly two decades after this approach was first introduced and failed to catch on. What's different this time around is the growing complexity and an emphasis on architectural improvements, as well as device scaling, particularly for AI/ML applications. Software is a critical component, and the more tightly integrate... » read more

Hybrid Emulation Takes Center Stage

By Ann Mutschler - 25 Jul, 2019 - Comments: 0

From mobile to networking to AI applications, system complexity shows no sign of slowing. These designs, which may contain multiple billion gates, must be validated, verified and tested, and it’s no longer possible to just throw the whole thing in a hardware emulator. For some time, emulation, FPGA-based prototyping, and virtual environments such as simulators have given design and verific... » read more

Optimize MATLAB C/C++ Code For HLS

By Zubair Wadood - 25 Jul, 2019 - Comments: 0

A common use case for high-level synthesis (HLS) is taking 3rd party generated or legacy C/C++ algorithms and converting the algorithm to a hardware implementation using an HLS compiler. This can present many challenges to the developer since there is little insight or understanding of the underlying code. In a recently published white paper, we examine how SLX FPGA is used to take a MATLAB... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?