tag: simulation

Maintaining Power Profiles At 10/7nm
By Ann Mutschler - 17 May, 2017 - Comments: 0

Understanding power consumption in detail is now a must-have of electronic design at 10nm and below, putting more pressure on SoC verification to ensure a device not only works, but meets the power budget. As part of this, the complete system must be run in a realistic manner — at the system-level — when the design and verification teams are looking at the effects of power during hardwar... » read more

Whatever Happened to High-Level Synthesis?
By Brian Bailey - 16 May, 2017 - Comments: 0

A few years ago, [getkc id="105" comment="high-level synthesis"] (HLS) was probably the most talked about emerging technology that was to be the heart of a new [getkc id="48" kc_name="Electronic System Level"] (ESL) flow. Today, we hear much less about the progress being made in this area. Semiconductor Engineering sat down to discuss this with Bryan Bowyer, director of engineering for high lev... » read more

Verification And The IoT
By Ed Sperling - 04 May, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss what impact the IoT will have on the design cycle, with Christopher Lawless, director of external customer acceleration in [getentity id="22846" e_name="Intel"]'s Software Services Group; David Lacey, design and verification technologist at Hewlett Packard Enterprise; Jim Hogan, managing partner at Vista Ventures; Frank Schirrmeister, senior group d... » read more

Can Formal Replace Simulation?
By Brian Bailey - 01 May, 2017 - Comments: 1

A year ago, [getentity id="22147" comment="Oski Technology"] achieved something that had never happened before. It brought together 15 of the top minds in [getkc id="33" kc_name="formal verification"] deployment and sat them down in a room to discuss the problems and issues they face and the ways in which they are attempting to solve those problems. Semiconductor Engineering was there to record... » read more

Rediscovering Coverage Insurance
By Dave Kelf - 27 Apr, 2017 - Comments: 0

When coverage comes up in conversation, if it comes up at all, it’s always a matter of car, home or health insurance. Coverage and functional verification are unlikely to be used in that discussion, or any other for that matter. That’s too bad because engineering groups grapple with when is enough verification enough, like some kind of coverage insurance. Oh sure, simulation and emulatio... » read more

The Democratization Of CFD
By Mentor, a Siemens Business - 26 Apr, 2017 - Comments: 0

“Democratization” is a buzzword that has been circulating around the Computational Fluid Dynamics (CFD) community for some time. In this White Paper, Keith Hanna and Ivo Weinhold of Mentor Graphicsdefine the issue, establish the facts, look at the pros and cons of various technology solutions being offered in the market today, and then suggest some pointers for the future as the CFD industr... » read more

Massive SoC Designs Open Doors To New Era In Simulation
By Cadence - 26 Apr, 2017 - Comments: 0

As system-on-chip (SoC) designs have grown in size, simulation technologies have had to evolve dramatically to keep pace. We’re now at an inflection point where both speed and capacity are essential and new simulation technologies are needed to meet the demands. In this paper, we’ll discuss how simulation has evolved and examine how new technologies such as the Cadence RocketSim Parallel Si... » read more

Creating Reliable SoCs For Safe ADAS Applications
By Ravi Ravikumar - 13 Apr, 2017 - Comments: 0

Every major automaker is in the process of bringing out autonomous vehicles with ADAS (advanced driver assistance systems). In addition to processors and embedded software, ADAS requires a variety of sensors – ultrasonic, camera, RADAR (radio detection and ranging), LIDAR (light detection and ranging), GPS and IR (infrared) – that are used to recognize signs, people, animals, other vehicles... » read more

Working With Custom Checkers In Dynamic Simulation Of Low Power Designs
By Progyna Khondkar - 13 Apr, 2017 - Comments: 0

Power-aware simulators can provide a wide range of automated assertions in the form of dynamic sequence checkers that cover every possible PA dynamic verification scenario. However, design specific PA verification complexities may arise from adoption of one or a multiple of power dissipation reduction techniques, from a multitude of design features — like UPF strategies — as well as from ta... » read more

What Is Portable Stimulus?
By Brian Bailey - 23 Mar, 2017 - Comments: 0

When [getentity id="22028" e_name="Accellera"] first formed the [getentity id="22863" comment="Portable Stimulus Working Group”] and gave it that name, I was highly concerned. I expressed my frustration that the name, while fitting with what most people thought [getkc id="10" kc_name="verification"] is about, does not reflect the true nature of the standard being worked on. In short, it is no... » read more

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