tag: simulation

FinFET Front-End-of-Line (FEOL) Process Integration With SEMulator3D
By Coventor - 19 Oct, 2016 - Comments: 0

Purely geometric scaling of transistors ended around the 90-nanometer (nm) era. Since then, most power/performance and area/cost improvements have come from structural and material innovations. Silicon-on-Insulator (SOI), first “partially depleted” and more recently “fully depleted” as well as embedded stressors, High-K / Metal-Gate (HKMG) and now FinFETs are examples of technology inno... » read more

Power Limits Of EDA
By Brian Bailey - 13 Oct, 2016 - Comments: 3

Power has become a major gating factor in semiconductor design. It is now the third factor in design optimization, along with performance, and is almost becoming more important than area. But there are limits to the amount of help that [getkc id="7" kc_name="EDA"] can provide with [getkc id="106" kc_name="power optimization"]. Power is not just an optimization problem. It is a design problem... » read more

Breakthrough Energy Innovation: Ambition And Urgency
By Ansys - 12 Oct, 2016 - Comments: 0

The easy answers to developing products for more sustainable energy designs have already been found, so only the toughest challenges remain to be solved. Innovative improvements to existing products are leading to increased complexity, while disruptive developments push engineers into uncharted design spaces. Either path — increased complexity or unknown territory — requires greater design ... » read more

Executive Insight: Wally Rhines
By Ed Sperling - 06 Oct, 2016 - Comments: 0

[getperson id="11694" p_name="Wally Rhines"], chairman and CEO of [getentity id="22017" e_name="Mentor Graphics"], sat down with Semiconductor Engineering to talk about changes in automotive electronics, IoT security issues, and how this affects semiconductor design. What follows are excerpts of that conversation. SE: In automotive, one of the big changes is that we are no longer dealing wit... » read more

Choosing Verification Engines
By Ed Sperling - 05 Oct, 2016 - Comments: 0

Emulation, simulation, FPGA prototyping and formal verification have very specific uses on paper, but the lines are becoming less clear as complexity goes up, more third-party IP is included, and the number of use cases and interactions of connected devices explodes. Ironically, the lines are blurring not for the most complex SoCs, such as those used in smart phones. The bigger challenge app... » read more

Heterogeneous System Challenges Grow
By Ann Mutschler - 03 Oct, 2016 - Comments: 0

As more types of processors are added into SoCs—CPUs, GPUs, DSPs and accelerators, each running a different OS—there is a growing challenge to make sure these compute elements interact properly with their neighbors. Adding to the problem is this mix of processors and accelerators varies widely between different markets and applications. In mobile there are CPUs, GPUs, video and crypto pr... » read more

Gaps In The Verification Flow
By Brian Bailey - 29 Sep, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the state of the functional verification flow with Stephen Bailey, director of emerging companies at [getentity id="22017" e_name="Mentor Graphics"]; [getperson id="11079" comment="Anupam Bakshi"], CEO of [getentity id="22168" e_name="Agnisys"]; [getperson id="11124" comment="Mike Bartley"], CEO of [getentity id="22868" e_name="Test and Verification... » read more

Tech Talk: Power Signoff
By Ed Sperling - 08 Sep, 2016 - Comments: 0

Ansys' Aveek Sarkar the challenges of power signoff at advanced process nodes, the impact of over-design, and what's necessary for sufficient coverage. [youtube vid=VQoT2KYW-AM] » read more

Simulating Composite Structures
By Ansys - 07 Sep, 2016 - Comments: 0

Composites provide new solutions for manufacturers looking for stronger, lighter and more cost-effective materials. At the same time, they pose new modeling and manufacturing challenges because of the nature of the materials. With the right simulation tools, designers can account for residual stresses, predict performance, analyze reliability and potential failures, optimize construction, and e... » read more

Optimization Challenges For 10nm And 7nm
By Brian Bailey - 06 Sep, 2016 - Comments: 0

Optimization used to be a simple timing against area tradeoff but not anymore. As we go to each new node, the tradeoffs become more complicated involving additional aspects of the design that used to be dealt with in isolation. Semiconductor Engineering sat down to discuss these issues with Krishna Balachandran, director of product management for low-power products at [getentity id="22032" e... » read more

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