tag: simulation

Dealing With The Data Glut
By Ann Mutschler - 11 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler Tools like emulation and simulation are an absolute necessity to design and verify today’s complex SoCs, but what happens when you want to do power analysis and the file sizes are too massive for the emulator to handle? Even with an emulator a five-minute mobile phone call could take three months. Understandably, this issue is causing pain to many design teams... » read more

Experts At The Table: The Trouble With Low-Power Verification
By Ed Sperling - 14 Mar, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power verification with Leah Clark, associate technical director at Broadcom; Erich Marschner, product marketing manager at Mentor Graphics; Cary Chin, director of marketing for low-power solutions at Synopsys; and Venki Venkatesh, senior director of engineering at Atrenta. What follows are excerpts of that conversat... » read more

Calculating Emulation’s Complex Cost Of Ownership
By Ed Sperling - 25 Oct, 2012 - Comments: 0

By Ann Steffora Mutschler Hardware emulation or hardware-assisted verification –whichever term you choose—has been around for decades. But until recently it has seen only modest adoption due to the high cost, long set-up time, power and IT requirements, among other things. But with simulation running out of steam between 50 and 100 million gates, this specialized hardware makes a ... » read more

Signal Integrity’s Growing Complexity
By Matt Elmore - 13 Sep, 2012 - Comments: 0

By Matt Elmore While in the market for a memory upgrade recently, I was surprised by the availability of commercial DDR memories. You can get 8GB of DDR3 memory, transferring 17GB/s, relatively inexpensively. The progress in memory design is outstanding. From smartphones to gaming PCs, quick communication between the IC and off-chip memory is key to enabling the performance we demand in the... » read more

Achieving Fast And Accurate Extraction Of 3D-IC Layout Structures
By Various Writers - 26 Jul, 2012 - Comments: 0

The electronics industry is devoting a lot of energy to exploring “More than Moore’s Law” approaches that drive continued value scaling through system integration, rather than (or in addition to) shrinking transistors. One of the most promising techniques is the creation of 3D-ICs using TSV structures. However, accurately modeling a 3D multi-die system requires tools that extract precise ... » read more

Emulation’s Winding Path To Success
By Ed Sperling - 28 Jun, 2012 - Comments: 0

By Ed Sperling Emulation was developed for verifying complex ICs when simulation was considered too slow. After more than a decade of very slow growth, however, sales have begun to ramp. There are several reasons for this shift. First, SoCs simply are becoming more complex, and the amount of verification that needs to be done to get a chip out the door can bring simulation to a crawl. Desig... » read more

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