tag: SIP

What Goes Wrong In Advanced Packages
By Ed Sperling - 24 Mar, 2021 - Comments: 1

Advanced packaging may be the best way forward for massive improvements in performance, lower power, and different form factors, but it adds a whole new set of issues that were much better understood when Moore's Law and the ITRS roadmap created a semi-standardized path forward for the chip industry. Different advanced packaging options — system-in-package, fan-outs, 2.5D, 3D-IC — have a... » read more

Addressing IC Hyperconvergence Design Challenges
By Aveek Sarkar - 11 Mar, 2021 - Comments: 0

Recently in an article titled “A Renaissance for Semiconductors,” my colleague Michael Sanie highlighted some of the trends that are driving next-generation product development. He detailed how designs targeting new applications are innovating through a combination of advanced process node technologies and heterogeneous integration of stacked die/3D/2.5D systems. Additionally, advanced vert... » read more

Chiplets For The Masses
By Brian Bailey - 03 Mar, 2021 - Comments: 2

Chiplets are a compelling technology, but so far they are available only to a select few players in the industry. That's changing, and the industry has taken little steps to get there, but timing for when you will be able to buy a chiplet to integrate into your system remains uncertain. While new fabrication nodes continue to be developed, scaling is coming to an end, be it for physical or e... » read more

Brazil Paves New Semiconductor Path
By Mark LaPedus - 22 Feb, 2021 - Comments: 3

After struggling to get its semiconductor industry off the ground for the last several years, Brazil finally may have found its place in the market with the development of IC design services, memory modules and packaging. Brazil exists well under the radar when it comes to semiconductors. But with little or no fanfare, the nation over the years has been trying to build fabs, assemble chips a... » read more

Shortages, Challenges Engulf Packaging Supply Chain
By Mark LaPedus - 18 Feb, 2021 - Comments: 0

A surge in demand for chips is impacting the IC packaging supply chain, causing shortages of select manufacturing capacity, various package types, key components, and equipment. Spot shortages in packaging surfaced in late 2020 and have since spread to other sectors. There are now a variety of choke points in the supply chain. Wirebond and flip-chip capacity will remain tight throughout 2021... » read more

Packaging Demands For RF And Microwave Devices
By Ken Molitor - 18 Feb, 2021 - Comments: 1

RF and microwave integrated circuits (ICs), monolithic microwave ICs (MMICs) and systems in package (SiPs) are vital for a wide range of applications. These include mobile phones, wireless local-area networks (WLANs), ultra-wideband (UWB), internet-of-things (IoT), GPS and Bluetooth devices. Moreover, RF-optimized packaging products and processes are essential to enabling the 5G ramp-up. RFI... » read more

Stronger, Better Bonding In Advanced Packaging
By Katherine Derbyshire - 21 Jan, 2021 - Comments: 1

System-in-package integrators are moving toward copper-to-copper direct bonding between die as the bond pitch goes down, making the solder used to connect devices in a heterogenous package less practical. In thermocompression bonding, protruding copper bumps bond to pads on the underlying substrate. In hybrid bonding, copper pads are inlaid in a dielectric, reducing the risk of oxidation. ... » read more

Wafer Prep Key To Thinning SiP
By Annette Teng - 17 Dec, 2020 - Comments: 0

In its ongoing push to create smaller, thinner, and denser chip packages, the semiconductor industry has intensified its focus on integrating separately manufactured components with different functionalities into systems-in-package (SIPs). Known as heterogeneous integration (HI), this approach now drives the industry’s roadmap for advancement. SiPs enable power-efficient, high-bandwidth conne... » read more

New RDL-First PoP Fan-Out Wafer-Level Package Process With Chip-to-Wafer Bonding Technology
By Amkor - 16 Dec, 2020 - Comments: 0

Fan-Out Wafer-Level Interposer Package-on Package (PoP) design has many advantages for mobile applications such as low power consumption, short signal path, small form factor, and heterogeneous integration for multifunctions. In addition, it can be applied in various package platforms, including PoP, System-in-Package (SiP), and Chip Scale Package (CSP). These advantages come from advanced inte... » read more

LDFO SiP For Wearables & IoT With Heterogeneous Integration
By Amkor - 02 Dec, 2020 - Comments: 0

Authors A. Martins*, M. Pinheiro*, A. F. Ferreira*, R. Almeida*, F. Matos*, J. Oliveira*, Eoin O´Toole*, H. M. Santos†, M. C. Monteiro‡, H. Gamboa‡, R. P. Silva* ‡Fraunhofer Portugal AICOS, Porto, Portugal †INESC TEC *AMKOR Technology Portugal, S.A. ABSTRACT The development of Low-Density Fan-Out (LDFO), formerly Wafer Level Fan-Out (WLFO), platforms to encompass the require... » read more

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