Building One Interface Subsystem For Multiple IoT SoCs

By Ralph Grundler - 11 May, 2017 - Comments: 0

When designing SoCs for Internet of Things (IoT) applications, designers quickly realize that their most efficient use of resources will result in chips that can address multiple end applications. Consumer products require connectivity or edge devices, and networking or enterprise companies are broadening their reach to home networking and cloud services, like remote processing, that complement... » read more

Software Driven Test Of FPGA Prototype

By Krzysztof Szczur - 27 Apr, 2017 - Comments: 0

Most everyone would agree how important FPGA prototyping is to test and validate an IP, sub-system, or a complete SoC design. Before the design is taped-out it can be validated at speeds near real operating conditions with physical peripherals and devices connected to it instead of simulation models. At the same time, these designs are not purely hardware, but these days incorporate a significa... » read more

Supporting CPUs Plus FPGAs (Part 3)

By Brian Bailey - 19 Apr, 2017 - Comments: 0

While it has been possible to pair a CPU and FPGA for quite some time, two things have changed recently. First, the industry has reduced the latency of the connection between them and second, we now appear to have the killer app for this combination. Semiconductor Engineering sat down to discuss these changes and the state of the tool chain to support this combination, with Kent Orthner, system... » read more

System-Level Testing

By Astronics - 10 Apr, 2017 - Comments: 0

This white paper on system-level testing for semiconductors. Covering the history and trends of system-level test for semiconductors, this solution brief discusses: The increasing complexities of testing advanced semiconductor integrated devices across a span of applications: automotive, mobile computing, wearables, and more; Semiconductor trends driving necessary shifts in testing method... » read more

Embedded FPGAs Come Of Age

By Ann Mutschler - 27 Feb, 2017 - Comments: 0

FPGAs increasingly are being viewed as a critical component in heterogeneous designs, ratcheting up their stature and the amount of attention being given to programmable devices. Once relegated to test chips that ultimately would be replaced by lower-power and higher-performance ASICs if volumes were sufficient, FPGAs have come a long way. Over the last 20 years programmable devices have mov... » read more

ECO Fill Can Rescue Your SoC Tapeout Schedule

By Vikas Gupta - 16 Feb, 2017 - Comments: 0

By Vikas Gupta and Bhavani Prasad Integrated circuit (IC) design and manufacturing is one of the most challenging engineering industries. As soon as a design engineer gets into “the groove” and feels comfortable taping out in a particular technology node, the next technology node shrink is already there to pose a new and greater set of challenges. While it almost goes without saying that... » read more

Tech Talk: Timing Closure

By Ed Sperling - 29 Dec, 2016 - Comments: 0

Arteris' George Janac talks about timing closure issues in advanced chips and why this has reared its head again for the first time in a decade. Related Stories Timing Closure Issues Resurface Adding more features and more power states is making it harder to design chips at 10nm and 7nm. » read more

System Performance Analysis At ARM

By Arm - 07 Dec, 2016 - Comments: 0

Performance analysis is a vital task in modern SoC design. An under-designed SoC may run too slowly to keep up with the demands of the system. An over-designed SoC will consume too much power and require more expensive IP blocks. At ARM we want to help our partners build SoCs that deliver the best performance within their power and area budgets. The simple truth is that this is more difficul... » read more

Embedded FPGAs Going Mainstream?

By Brian Bailey - 27 Oct, 2016 - Comments: 0

Systems on chip have been made with many processing variants ranging from general-purpose CPUs to DSPs, GPUs, and custom processors that are highly optimized for certain tasks. When none of these options provide the necessary performance or consumes too much power, custom hardware takes over. But there is one type of processing element that has rarely been used in a major SoC— the [gettech id... » read more

Coherency: The New Normal In SoCs

By NetSpeed Systems - 26 Oct, 2016 - Comments: 0

We are not far from devices each handling 100 teraflops of compute, billions of pixels of display, hundreds of gigabits of connectivity, and terabytes of storage. Compared with current state-of-the-art mobile SoCs, these are increases of one or two orders of magnitude — at similar or preferably lower power consumption. SoC design is changing to meet this challenge. Multicore architecture i... » read more

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tag: SoC

Building One Interface Subsystem For Multiple IoT SoCs

Software Driven Test Of FPGA Prototype

Supporting CPUs Plus FPGAs (Part 3)

System-Level Testing

Embedded FPGAs Come Of Age

ECO Fill Can Rescue Your SoC Tapeout Schedule

Tech Talk: Timing Closure

System Performance Analysis At ARM

Embedded FPGAs Going Mainstream?

Coherency: The New Normal In SoCs

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