tag: software

Interface Additions To The e Language For Effective Communication With SystemC TLM 2.0 Models
By Various Writers - 23 Aug, 2012 - Comments: 0

The last several years have seen strong adoption of transaction-level models using SystemC TLM 2.0. Those models are used for software validation and virtual prototyping. For functional verification, TLMs have a number of advantages—they are available earlier, they allow usersto divide their focus on verifying functionality and protocol/timing details, they enable higher level reuse, and they... » read more

Development of Complex Multicore Systems: Tracing Challenges and Concept (Part One)
By Various Writers - 23 Aug, 2012 - Comments: 0

This white paper is the first paper of a two-part Mentor Embedded multicore white paper series. In this paper, the challenges software developers face when developing, debugging, and validating software applications for a complex multicore system will be discussed. The paper also highlights some of the questions around hardware resource usage, tracing aids, tracing domains, and concepts for col... » read more

The Seven Layers Of Hardware-Software Debug
By Frank Schirrmeister - 22 Aug, 2012 - Comments: 0

By Frank Schirrmeister [caption id="attachment_9863" align="alignnone" width="639"] Seven Layers of Hardware/Software Debug[/caption] Of course I will be in trouble once this blog is posted. This post is about hardware/software debug,  and I tried to layer a set of different levels for the scope and applicability of debug. I counted seven layers, but I am sure that one may be able to arr... » read more

Experts At The Table: Coherency
By Ed Sperling - 17 Aug, 2012 - Comments: 0

System-Level Design sat down to discuss coherency with Mirit Fromovich, principal solutions engineer at Cadence; Drew Wingard, CTO of Sonics; Mike Gianfagna, vice president of marketing at Atrenta, and Marcello Coppola, technical director at STMicroelectronics. What follow are excerpts of that conversation. SLD: We’ve been hearing a lot about Wide I/O. Why is it so important and what effec... » read more

Experts At The Table: Coherency
By Ed Sperling - 17 Aug, 2012 - Comments: 0

System-Level Design sat down to discuss coherency with Mirit Fromovich, principal solutions engineer at Cadence; Drew Wingard, CTO of Sonics; Mike Gianfagna, vice president of marketing at Atrenta, and Marcello Coppola, technical director at STMicroelectronics. What follow are excerpts of that conversation. SLD: We’ve been hearing a lot about Wide I/O. Why is it so important and what effec... » read more

Moore’s Legacy
By Ed Sperling - 08 Aug, 2012 - Comments: 0

Low-Power High-Performance Engineering talks with MIPS' Mark Throndson, product marketing director, and Ranganathan "Suds" Sudhakar, chief architect, about Moore's Law, multicore chips, software, coherency and the insatiable global demand for speed. [youtube vid=VfvfYSkPpcs] » read more

printf(“I Like”);
By Achim Nohl - 26 Jul, 2012 - Comments: 0

By Achim Nohl Debugging software by adding printf statements in the code is not considered the cleanest and most advanced debugging approach, but when you are searching for the root cause of a problem you often look to the debugging method you are most familiar with and can apply easily. The hurdle of setting up a complex debug or trace tool is counterproductive when dealing with schedule c... » read more

Who Calls The Shots?
By Kurt Shuler - 26 Jul, 2012 - Comments: 0

By Kurt Shuler Who REALLY calls the shots in chip design today? That sounds like a stupid question. Who really calls the shots in chip design today? Well, chip designers of course. But you’re wrong if you mean to say that the traditional semiconductor manufacturers are the ones who always do all the hefty work of chip design, including determining requirements, performing technical tra... » read more

Experts At The Table: Pain Points
By Ed Sperling - 20 Jul, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down with Vinod Kariat, a Cadence fellow; Premal Buch, vice president of software engineering at Altera; Vic Kulkarni, general manager of Apache Design; Bernard Murphy, CTO at Atrenta, and Laurent Moll, CTO at Arteris. What follows are excerpts of that conversation. LPHP: With stacked die it’s no longer one company making an SoC. W... » read more

Experts At The Table: Does 20nm Break System-Level Design?
By Ed Sperling - 13 Jul, 2012 - Comments: 1

By Ann Steffora Mutschler System-Level Design sat down to discuss design at 20nm with Drew Wingard, chief technology officer at Sonics; Kelvin Low, deputy director of product marketing at GlobalFoundries, Frank Schirrmeister, group director of product marketing for system development in the system and software realization group at Cadence; and Mike Gianfagna, vice president of marketing at Atr... » read more

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