tag: Sonics

The Return Of Body Biasing
By Ann Mutschler - 15 Nov, 2017 - Comments: 1

Body biasing is making a comeback across a wide swath of process nodes as designers wrestle with how to build mobile devices with more functionality and longer battery life. Consider an ultra-low-power IoT device with a wireless sensor, for example, which is meant to last for years without changing a battery. Body biasing can be used to create an ultra-low-leakage sleep state. “In that ... » read more

New Drivers For I/O
By Brian Bailey - 13 Nov, 2017 - Comments: 0

Interface standards are on a tear, and new markets are pushing the standards in several directions at the same time. The result could be a lot more innovation and some updates in areas that looked to be well established. Traditionally, this has been a sleepy and predictable part of the industry with standards bodies producing updates to their interfaces at a reasonable rate. Getting data int... » read more

Lots Of Little Knobs For Power
By Ann Mutschler - 09 Nov, 2017 - Comments: 3

Dynamic power is becoming a much bigger worry at new nodes as more finFETs are packed on a die and wires shrink to the point where resistance and capacitance become first-order effects. Chipmakers began seeing dynamic power density issues with the first generation of [getkc id="185" kc_name="finFETs"]. While the 3D transistor structures reduced leakage current by providing better gate contro... » read more

Mixed Messages For Mixed-Signal
By Brian Bailey - 09 Nov, 2017 - Comments: 1

There is no such thing as a purely digital design at advanced nodes today. Even designs that have no [getkc id="37" kc_name="analog"] content are likely relying on [getkc id="38" kc_name="mixed-signal"] components such as SerDes for communications, or voltage regulators for adaptive power control. But the days of purposely attempting to integrate everything including analog and RF onto a single... » read more

Blog Review: Nov. 8
By Jesse Allen - 08 Nov, 2017 - Comments: 0

Synopsys' Eric Huang digs in to what's new with USB 3.2 and what's achieved by preserving the existing PHY signaling speeds. In a video, Mentor's Colin Walls provides tips on how to write debuggable and maintainable embedded code. Cadence's Paul McLellan listens in on a talk by Andrew Kahng of UC San Diego on the problem of scaling and why machine learning can improve EDA tools. Rambus... » read more

How To Handle Concurrency
By Brian Bailey - 30 Oct, 2017 - Comments: 3

The evolution of processing architectures has solved many problems within a chip, but for each problem solved another one was created. Concurrency is one of those issues, and it has been getting much more attention lately. While concurrency is hardly a new problem, the complexity of today’s systems is making it increasingly difficult to properly design, implement and verify the software an... » read more

The Week In Review: Design
By Jesse Allen - 27 Oct, 2017 - Comments: 0

M&A PLDA is divesting its Reflex CES brand. The FPGA board maker will become wholly managed by its own management and investment teams. In 2015, Reflex CES took over the hardware businesses of PLDA, including FPGA-based boards and the System-on-Module product lines. Tools Mentor uncorked a new tool for in-system test and diagnosis of automotive ICs. Tessent MissionMode provides infrast... » read more

Move Data Or Process In Place?
By Brian Bailey - 26 Oct, 2017 - Comments: 0

Should data move to available processors or should processors be placed close to memory? That is a question the academic community has been looking at for decades. Moving data is one of the most expensive and power-consuming tasks, and is often the limiter to system performance. Within a chip, Moore's Law has enabled designers to physically move memory closer to processing, and that has rema... » read more

Trimming Waste In Chips
By Brian Bailey - 12 Oct, 2017 - Comments: 0

Extra circuitry costs money, reduces performance and increases power consumption. But how much can really be trimmed? When people are asked that question they either get defensive or they see it as an opportunity to show the advantages of their architecture, design process or IP. The same holds true for IP suppliers. Others point out that the whole concept of waste is somewhat strange, becau... » read more

System Coverage Undefined
By Brian Bailey - 28 Sep, 2017 - Comments: 1

When is a design ready to be taped out? That has been one of the toughest questions to confront every design team, and it's the one verification engineers lose sleep over. Exhaustive [getkc id="56" kc_name="coverage"] has not been possible since the 1980s. Several metrics and methodologies have been defined to help answer the question and to raise confidence that important aspects of a block... » read more

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