The Week In Review: Design

PLDA divests Reflex CES; in-system test for automotive; security IP; superconductor tools.


PLDA is divesting its Reflex CES brand. The FPGA board maker will become wholly managed by its own management and investment teams. In 2015, Reflex CES took over the hardware businesses of PLDA, including FPGA-based boards and the System-on-Module product lines.

Mentor uncorked a new tool for in-system test and diagnosis of automotive ICs. Tessent MissionMode provides infrastructure for system software-based access to any test and diagnosis capabilities integrated within an automotive chip. An in-system test (IST) controller integrated into the chip drives an internal IEEE 1687 (IJTAG) access network to communicate to any IJTAG-compliant IP. The IST controller supports all Tessent DFT products including memory BIST, logic BIST, and EDT logic. The IST controller also provides a communication path to outside the chip through a generic CPU interface.

Aldec released a new prototyping board based on Xilinx Zynq UltraScale+ MPSoC. Targeted at embedded vision applications such as ADAS, surveillance and multimedia, the board features Quad ARM Cortex-A53, Dual ARM Cortex-R5, UltraScale+ PL with Video Codec H.265/H.264, HDMI IN 2.0, HDMI OUT 2.0, 256MB NAND Flash, 4x USB 3.0, 2x FMC connector, QSFP+, Wi-Fi and Bluetooth.

Imperas announced models and virtual platforms for the Arm Cortex-A32, Cortex-A35, Cortex-A55, Cortex-A73, Cortex-A75 processors, including ARMv8.1 and ARMv8.2 support, enabling simulation, software debug, verification, analysis, and profiling (VAP) tools, and OS (Linux) booting on the virtual platforms.

Cadence made its Xcelium simulator available for Arm-based servers. Cadence cited significant power and capacity benefits from running on Arm servers, and says the latest simulator provides up to 2X speedup for single-core, and 3X to 10X speedup for multi-core simulation tasks compared to previous versions.

Arm launched two new secure IP components. The first is a new family of highly integrated security subsystems providing on-die, smartcard-level security, which currently targets applications requiring high levels of isolation and security, such as LPWA communication, storage, and automotive. The second is a secure debug channel to police debug accesses into the system. Arm also introduced a common industry framework for building secure connected devices. Called Platform Security Architecture, it focuses on providing IoT threat models and security analysis as well as hardware and firmware architecture specifications defining a best practice approach for designing endpoint devices.

eMemory released upgraded EEPROM IP that supports over 500,000 rewrite cycles and meets the automotive industry’s standards of 10-year data retention at 150°C operation. The memory IP is fully compatible with standard logic and Bipolar-CMOS-DMOS (BCD) process and has been silicon verified at 0.18um/5V process.

Silvaco debuted an Arm-based I3C sensor IP subsystem core. The subsystem utilizes an Arm Cortex M0 CPU, and includes a I3C Dual Role Master controller core with high data rate DDR modes, in-band-interrupts and a complete slave to enable dynamic master/slave role switching

Hardent uncorked VESA DSC 1.1 encoder IP as part of a new line of ASIL-B ready ISO 26262 certified IP products for safety-critical automotive display applications. The IP includes self-check, control output diagnostics, and RAM ECC.

The Intelligence Advanced Research Projects Activity (IARPA) awarded Synopsys a multi-year research and development contract to advance EDA tool flows for Superconducting Electronics (SCE) as part of its SuperTools project. The project aims to develop tools for cryogenic, high-performance computing beyond CMOS. SCE company HYPRES will consult on developing libraries, circuits, IP processing and testing. Guiding the project will be academic experts from Stony Brook University, Yokohama National University, and the University of Rochester.

NetSpeed and UltraSoC integrated their solutions, including embedded UltraSoC monitors, debug ports, and analytics, to work seamlessly with NetSpeed on-chip network IP.

Sonics and Moortec integrated Sonics’ energy processing units with Moortec’s embedded temperature sensors to enable temperature-compensated, dynamic voltage and frequency scaling (DVFS) in chip designs intended for power-sensitive devices.

SiFive adopted Synopsys’ verification platform for simulation, verification IP, debug, static verification and formal coverage closure of its customized RISC-V processors and SoCs.

Ansys and Rescale launched a program to give startups access to Ansys engineering simulation tools from a browser window with a standard Internet connection using Rescale’s web-based cloud platform for big compute.

The PCIe 4.0 Specification Version 1.0 has been released. PCIe 4.0 supports 16GT/s data rates with flexible lane width configurations. Other features include extended tags and credits for service devices, lane margining, and improved I/O virtualization and platform integration. The spec is available from SCI-SIG.

Rambus released third quarter financial results with revenue of $99.1 million, up 10% from $89.9 million in the same quarter last year. On a GAAP basis, income per share for the quarter stood at $0.07, up 75% from $0.04 in Q3 2016, while non-GAAP income per share was $0.19, up 19% from $0.16. Next quarter, the company expects revenue between $98 million and $104 million.

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