Why The Next Couple Process Nodes Are So Critical

By Ed Sperling - 14 Aug, 2014 - Comments: 0

In the greater scheme of things, one process node doesn't matter all that much. In fact, it has become common practice for big chipmakers to skip nodes for some of their chips as power issues becoming increasingly complex, time-to-market windows shrink and leapfrogging is viewed as a way to maximize resources while remaining über-competitive. But the next process node, and certainly the nex... » read more

Executive Insight: Gideon Wertheizer

By Ed Sperling - 13 Aug, 2014 - Comments: 0

SE: From your standpoint, what’s the next big thing? Wertheizer: The industry was driven in the past few years by the structure the smartphone created. It looks like this area is about to grow. What’s changing is the integration of the smartphone with other applications. The smartphone is now a hub of entertainment and productivity with many devices connecting directly or indirectly to i... » read more

Executive Insight: Taher Madraswala

By Ed Sperling - 11 Aug, 2014 - Comments: 1

Semiconductor Engineering sat down with Taher Madraswala, president of Open-Silicon, to talk about future challenges, opportunities and changes. What follows are excerpts of that interview. SE: What worries you most? Madraswala: What worries me at the industry-level is the growing effect that business constraints are having on product innovation. We’ve done a very good job of advancing ... » read more

Improving 2.5D Components

By Ed Sperling - 07 Aug, 2014 - Comments: 1

A lot of attention is being focused on improving designs at established, well-tested nodes where processes are mature, yields are high, and costs are under control. So what does this mean to stacking die? For 2.5D architectures, plenty. For 3D, probably not much. Here’s why: The advantage of 2.5D is that it can utilize dies created at whatever node makes sense. While the initial discuss... » read more

When Will 2.5D Cut Costs?

By Brian Bailey - 07 Aug, 2014 - Comments: 2

There is a constant drive to reduce costs within the semiconductor industry and, up until now, [getkc id="74" comment="Moore's Law"] provided an easy path to enable this. By adopting each smaller node, transistors were cheaper, but that is no longer the case, as explained in a recent article. The industry will need to find new technologies to make this happen and some people are looking towards... » read more

Established Nodes Getting New Attention

By Ed Sperling - 07 Aug, 2014 - Comments: 0

As the price of shrinking features increases below 28nm, there has been a corresponding push to create new designs at established nodes using everything from near-threshold computing to back biasing and mostly accurate analog sensors. The goals of power, performance and cost haven’t changed, but there is a growing realization among many chipmakers that the formula can be improved upon with... » read more

Improving The PPA Equation

By Ed Sperling - 24 Jul, 2014 - Comments: 0

The next generation of semiconductors may look very much like the existing generation. But like the old Porsche ads that required arrows to point to the improvements, because from the outside things basically looked the same, there should be plenty of impressive stuff inside. As the cost per transistor continues to rise at advanced nodes, the focus for most companies is no longer about shrin... » read more

EDA’s Hedge Plays

By Ed Sperling - 24 Jul, 2014 - Comments: 0

While 14/16nm process technologies with finFETs and double patterning have pushed complexity to new heights, the move to 10nm fundamentally will change a number of very basic elements of the design through manufacturing flow—and EDA vendors will be caught in the middle of having to make hard choices between foundries, processes, packaging approaches, and potentially which markets to serve. ... » read more

2.5/3D IC – Do We Have Liftoff?

By Mike Gianfagna - 24 Jul, 2014 - Comments: 2

The challenges of Moore’s law scaling at advanced technolgy nodes are well documented. I won’t repeat them here. The benefits of “more than Moore” scaling (i.e., 2.5D and 3D ICs) are also well-known. This technology has shown great promise to provide an alternate path for large-scale integration. The technology has seen a lot of research effort, infrastructure support, standards develop... » read more

Foundries Versus OSATs

By Ed Sperling - 24 Jul, 2014 - Comments: 2

Since the 1990s, commercial foundries have ruled semiconductor manufacturing while the [getkc id='83' comment='OSAT'] providers (OSATs) have dominated IC packaging and testing. But as the industry moves toward stacked die over the next couple of years, and big foundries see a chance to expand their reach, the stage is set for an all-out war. There is much at stake on both sides. Foundries g... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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