tag: stacked die

Improving 2.5D Components
By Ed Sperling - 07 Aug, 2014 - Comments: 1

A lot of attention is being focused on improving designs at established, well-tested nodes where processes are mature, yields are high, and costs are under control. So what does this mean to stacking die? For 2.5D architectures, plenty. For 3D, probably not much. Here’s why: The advantage of 2.5D is that it can utilize dies created at whatever node makes sense. While the initial discuss... » read more

When Will 2.5D Cut Costs?
By Brian Bailey - 07 Aug, 2014 - Comments: 2

There is a constant drive to reduce costs within the semiconductor industry and, up until now, [getkc id="74" comment="Moore's Law"] provided an easy path to enable this. By adopting each smaller node, transistors were cheaper, but that is no longer the case, as explained in a recent article. The industry will need to find new technologies to make this happen and some people are looking towards... » read more

Established Nodes Getting New Attention
By Ed Sperling - 07 Aug, 2014 - Comments: 0

As the price of shrinking features increases below 28nm, there has been a corresponding push to create new designs at established nodes using everything from near-threshold computing to back biasing and mostly accurate analog sensors. The goals of power, performance and cost haven’t changed, but there is a growing realization among many chipmakers that the formula can be improved upon with... » read more

Improving The PPA Equation
By Ed Sperling - 24 Jul, 2014 - Comments: 0

The next generation of semiconductors may look very much like the existing generation. But like the old Porsche ads that required arrows to point to the improvements, because from the outside things basically looked the same, there should be plenty of impressive stuff inside. As the cost per transistor continues to rise at advanced nodes, the focus for most companies is no longer about shrin... » read more

EDA’s Hedge Plays
By Ed Sperling - 24 Jul, 2014 - Comments: 0

While 14/16nm process technologies with finFETs and double patterning have pushed complexity to new heights, the move to 10nm fundamentally will change a number of very basic elements of the design through manufacturing flow—and EDA vendors will be caught in the middle of having to make hard choices between foundries, processes, packaging approaches, and potentially which markets to serve. ... » read more

2.5/3D IC – Do We Have Liftoff?
By Mike Gianfagna - 24 Jul, 2014 - Comments: 2

The challenges of Moore’s law scaling at advanced technolgy nodes are well documented. I won’t repeat them here. The benefits of “more than Moore” scaling (i.e., 2.5D and 3D ICs) are also well-known. This technology has shown great promise to provide an alternate path for large-scale integration. The technology has seen a lot of research effort, infrastructure support, standards develop... » read more

Foundries Versus OSATs
By Ed Sperling - 24 Jul, 2014 - Comments: 2

Since the 1990s, commercial foundries have ruled semiconductor manufacturing while the [getkc id='83' comment='OSAT'] providers (OSATs) have dominated IC packaging and testing. But as the industry moves toward stacked die over the next couple of years, and big foundries see a chance to expand their reach, the stage is set for an all-out war. There is much at stake on both sides. Foundries g... » read more

IP And FinFETs At Advanced Nodes
By Ed Sperling - 21 Jul, 2014 - Comments: 2

Semiconductor Engineering sat down to discuss IP and finFETs at advanced nodes with Warren Savage, president and CEO of IPextreme; Aveek Sarkar, vice president of engineering and product support at Ansys-Apache; Randy Smith, vice president of marketing at Sonics, and Bernard Murphy, CTO of Atrenta;. What follows are excerpts of that conversation. SE: What happens with the next revs of finFET... » read more

Executive Insight: Ajoy Bose
By Ed Sperling - 21 Jul, 2014 - Comments: 1

SE: What keeps you awake at night? Bose: What I worry about more than anything else is the need for us (at Atrenta) to show growth on an ongoing basis. A company’s challenges change with the lifecycle of that company. In the early days you worry about survival and trying to establish yourself in the industry. Fortunately, Atrenta is a bigger company today, so the nature of the concerns has c... » read more

1-on-1 With Intel’s Foundry Chief
By Mark LaPedus - 17 Jul, 2014 - Comments: 1

By Mark LaPedus & Ed Sperling Semiconductor Engineering sat down to discuss foundry trends, IC scaling, chip-packaging and other topics with Sunit Rikhi, vice president of the Technology and Manufacturing Group at Intel and general manager of Intel’s Custom Foundry unit. SE: Where is Intel at in the foundry business today? Rikhi: We started with a very narrow set of customers. Now, we... » read more

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