Why The Next Couple Process Nodes Are So Critical

What chipmakers decide in the next few years will determine the future and fate of large foundries.


In the greater scheme of things, one process node doesn’t matter all that much. In fact, it has become common practice for big chipmakers to skip nodes for some of their chips as power issues becoming increasingly complex, time-to-market windows shrink and leapfrogging is viewed as a way to maximize resources while remaining über-competitive.

But the next process node, and certainly the next-couple nodes, may radically redefine the semiconductor industry as we know it, particularly for the big foundries. For one thing, there are questions about how quickly leading-edge customers will adopt finFETs. To some extent that is based on lithography. Multi-patterning is expensive and complicated, and done wrong it can have disastrous effects on yield. Even done right, yields will still drop for complex chips, according to Gartner’s numbers.

EUV remains a big question mark in all of this. After billions of dollars of investment, it still isn’t ready for prime time. If it suddenly does become available, no one is sure how expensive it will be. Even with EUV, multi-patterning still may be the least-cost alternative for shrinking features.

Another question that remains to be answered is how stacked die will fit into this equation. If yields are better using smaller die, and overall costs can be brought down by stacking them, then it’s highly likely that this approach will kick into high gear after 14nm. Companies already are working on 2.5D approaches, but the real architectural gains in terms of power and performance will happen with logic on logic in full 3D configurations, using fat pipes—most likely TSVs—over short distances, and more rational utilization of on-chip or in-package resources such as memory or processor elements.

And finally, there is a question of just how much established nodes—28nm and above—can be improved. Near-threshold computing, dynamic voltage frequency and scaling, back biasing, FD-SOI, and better process technology can make staying at older nodes using single patterning and 193nm immersion lithography very attractive for a long time.

All of which leads back to the original point of this article. For chipmakers, one node may not make much of a difference. For foundries it may make a world of difference, depending on how much they’ve invested in new technology. Intel, GlobalFoundries, Samsung, TSMC and UMC are all playing a very high-stakes game of poker with 14/16nm and 10nm, and it’s unlikely that all of them will have a winning hand.

This game will likely last for at least a couple years, and maybe as long as four to six years, but in the end some of the players will have to leave the high-stakes game and figure out a different way to win. As the number of chipmakers working at the leading edge continues to shrink, the number of foundries will have to shrink with them. And those who have a hiccup in their investment strategies—too much capacity when it’s not needed, or too little when it is—could find themselves in deep trouble very quickly.

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