Rethinking Differentiation

By Ed Sperling - 28 Aug, 2015 - Comments: 0

Differentiation is becoming more difficult, more time-consuming, and in some cases much more expensive for chipmakers. The traditional metrics of faster performance, lower power and less area/cost, which are leftovers from the PC era, no longer are a guarantee of success despite the fact that they are still baseline metrics for many designs. Even new metrics such as ecosystem completeness, w... » read more

Electronics Butterfly Effect

By Brian Bailey - 27 Aug, 2015 - Comments: 1

Everyone has heard of the butterfly effect where a small change in a non-linear system can result in large difference in an outcome. For the past 40 years, the electronics industry has approximated a linear system, fed primarily by Moore’s Law. The incremental changes available at each new process node have led us to make incremental changes and improvements in many aspects of the design, its... » read more

Interconnect Challenges Grow

By Mark LaPedus - 20 Aug, 2015 - Comments: 1

It’s becoming apparent that traditional chip scaling is slowing down. The 16nm/14nm logic node took longer than expected to unfold. And the 10nm node and beyond could suffer the same fate. So what’s the main cause? It’s hard to pinpoint the problem, although many blame the issues on lithography. But what could eventually hold up the scaling train, and undo Moore’s Law, is arguably t... » read more

Challenges At Advanced Nodes

By Ed Sperling - 19 Aug, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss finFETs, 22nm FD-SOI and how the how the market will segment over the next few years with Marie Semeria, CEO of [getentity id="22192" e_name="Leti"]; Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Paul Boudre, CEO of Soitec; and Subramani Kengeri, vice president of global ... » read more

2.5D Creeps Into SoC Designs

By Ed Sperling - 13 Aug, 2015 - Comments: 0

A decade ago top chipmakers predicted that the next frontier for SoC architectures would be the z axis, adding a third dimension to improve throughput and performance, reduce congestion around memories, and reduce the amount of energy needed to drive signals. The obvious market for this was applications processors for mobile devices, and the first companies to jump on the stacked die bandwag... » read more

Executive Insight: Aart de Geus

By Ed Sperling - 10 Aug, 2015 - Comments: 0

Aart de Geus, chairman and co-CEO of Synopsys, sat down with Semiconductor Engineering to talk about acquisitions, software and EDA. What follows are excerpts of that interview, which was conducted in front of a live audience at DAC. SE: A lot of Synopsys' investments are moving in a new direction, namely software. Why is that becoming so important to your company? De Geus: It's not a dif... » read more

Executive Insight: Wally Rhines

By Ed Sperling - 01 Jul, 2015 - Comments: 0

Wally Rhines, chairman and CEO of Mentor Graphics, sat down with Semiconductor Engineering to talk about what's changing across a wide swath of the industry, where the new opportunities will be, when security will become a real opportunity for EDA, and why Moore's Law will die but progress will continue forever. SE: Looking back over the past year, what's changed and where are the possible r... » read more

The Future Of Moore’s Law

By Ed Sperling - 29 Jun, 2015 - Comments: 1

Semiconductor Engineering sat down to discuss the future of Moore's Law with Jan Rabaey, Donald O. Pederson distinguished professor at [getentity id="22165" comment="UC Berkeley"]; Lucio Lanza, managing director of Lanza techVentures; Subramani Kengeri, vice president of advanced technology architecture at [getentity id="22819" comment="GlobalFoundries"]; Charlie Cheng, CEO of [getentity id="2... » read more

Intel Plus Altera

By Ed Sperling - 25 Jun, 2015 - Comments: 0

Since the Intel-Altera deal reached the handshake phase earlier this month, there have been a lot of theories being forwarded and a lot of questions being raised. And there have been very few answers, in part because the deal isn't finalized yet and in part because this marriage will take time to play out in the market—maybe years. But along with the GlobalFoundries-IBM pairing, this is th... » read more

IP Market Shifts Direction

By Ed Sperling - 03 Jun, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss intellectual property changes and challenges with Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Navraj Nandra, senior director of marketing for DesignWare analog and MSIP at [getentity id="22035" e_name="Synopsys"]; Kurt Shuler, vice president of marketing at [getentity i... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: stacked die