New Options For Power

There’s no single solution, but lots of little things can make a big difference.


Chipmakers have been talking for years about the next big breakthrough in battery technology, low-power architectures and energy harvesting. So far, none of them has made their job any easier.

Batteries empty out too quickly, and the technology for improving the amount of energy that can be stored don’t improve fast enough—or safely enough when they do show big improvements—to make a big enough impact. That’s particularly true as more and more features are continually added into devices. A smartphone typically runs out of power in a day of active use, while a smart watch will last several days. The goal of going weeks between charges is so far off on the horizon that no one even talks about it anymore.

Energy harvesting, which is the subject of much research, remains a work in progress. While it’s possible to draw small amounts of energy from movement, ambient radio waves, and even body heat, the concept of a single low-power duty cycle is well outside the boundaries of most applications.

Even the march to the next process node is no longer a guarantee that it will use less power. As RC delay increases for increasingly small interconnects, new materials will be required. That’s no simple swap-out, though. The last big material shift was the addition of copper interconnects at 130nm, and it slowed down the progress of Moore’s Law for months. Adding III-V materials and new oxides is even more difficult. For one thing, not all of these materials are readily available. For another, they are softer and harder to work with, meaning yields will suffer in the short term.

But even if those materials do become available and reach widespread use, there’s no guarantee power consumption will be any lower. The number of techniques needed to reduce dynamic power will increase significantly at each new process node, and leakage current will begin to climb again as the processes shrink into single-digit nanometers. And that’s assuming that EUV lithography or directed self-assembly are ready to pattern masks, because trying to do low-power designs using octa-patterning is not a pleasant thought.

Silicon photonics is one option under development for lowering heat. New memory types and controllers and 2.5D and 3D stacked die could help, as well. There has been significant progress on all sides. If the photonics can be embedded into silicon at a reasonable cost, then huge progress can be made in terms of reducing heat and improving speed. Light moves faster than electrons and it can carry more data.

All of these advancements are important, and many of them will begin showing up in some designs over the next few years. Memory using stacked die already is a reality, and 2.5D architectures are slowly making their way into the chip ecosystem, which reduces the power needed to drive signals because there is less resistance and distances are shorter. But what really gets interesting is when these different options become mature enough that several of them get incorporated into a single design.

As many engineers have commented over the past few years, there is no silver bullet when it comes to power. But lots of smaller silver pellets can make as big an impact as a single bullet if aimed in the right direction, and there is enough progress in multiple areas that some of this will begin showing up in the next few years.

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