Integrating Data From Design, Manufacturing, And The Field


Chip design is starting to include more options to ensure chips behave reliably in the field, boosting the ability to tweak both hardware and software as chips age. The basic problem is that as dimensions become smaller, and as more features are added into devices — especially with heterogeneous assemblies of chiplets running some type of AI — the potential for thermally induced structur... » read more

LLE-Aware Design Methodology To Avoid Timing And Power Pessimism


As chips move to ever-finer geometries, the active region (diffusion) shapes of neighboring cells can impact timing analysis and power calculations for the entire design. The LLE (Local Layout Effect) impact must be measured, but the impact is reflected very conservatively using conventional approaches. This paper describes a LLE-aware design methodology that mitigates the conservatism of co... » read more

Blog Review: Mar. 12


Cadence's P. Saisrinivas explains the relationship between drive strength and cell delay and why it is key to choose the appropriate drive strength to meet timing constraints while minimizing power and area. Siemens' Daniel Berger and Dirk Hartmann tackle the readout problem of accurately measuring the state of a quantum system after it has undergone a quantum computation, which becomes incr... » read more

Speeding Down Memory Lane With Custom HBM


With the goal of increasing system performance per watt, the semiconductor industry is always seeking innovative solutions that go beyond the usual approaches of increasing memory capacity and data rates. Over the last decade, the High Bandwidth Memory (HBM) protocol has proven to be a popular choice for data center and high-performance computing (HPC) applications. Even more benefit can be rea... » read more

Automation And AI Improve Failure Analysis


When a chip malfunctions it’s the job of the failure analysis engineer to determine how it failed or significantly deviated from its key performance metrics. The cost of failure in the field can be huge in terms of downtime, recalls, damage to a company’s reputation, and more. For these reasons, chipmakers take customer returns very seriously, focusing resources to quickly get to the bot... » read more

Cutting IC Manufacturing Costs By Combining Data


Experts at the Table: Semiconductor Engineering sat down to discuss the benefits of incorporating financial data into fab floor decision-making, including what kind of cost data is most useful, with Dieter Rathei, CEO of DR Yield; Jon Holt, senior director of product management at PDF Solutions, Alex Burlak, vice president of advanced analytics and test at proteanTecs; and Dirk de Vries, techni... » read more

Multi-Die Health And Reliability: UCIe Advances


Although multi-die designs — an increasingly popular approach for integrating heterogeneous and homogenous dies into a single package — help resolve problems related to chip manufacturing and yield, they introduce a host of complexities and variables that must be addressed. In particular, designers must work diligently to ensure the health and reliability of their multi-die chip throughout ... » read more

Secure Interfaces for Critical Semiconductor Applications


Security is now a concern for nearly all semiconductors in nearly all applications. Once of high interest mostly for military and financial systems, both the increasingly connected world and the plethora of existing security threats have changed the landscape dramatically. Every aspect of electronic system design—hardware, firmware, and software—has its own sets of risks and requirements to... » read more

Automakers Grapple With Fundamental Tech Changes


Automotive OEMs are wrestling with a stack of changes that affect every part of their business and technology, from threats of tariffs and shifting geopolitical alliances, to new vehicle architectures, tighter market windows, and a fundamental reordering of relationships and priorities between OEMs and their suppliers. There is no consistency to these developments or a best path to solving t... » read more

Verification Experts Vs. Generalists


Experts At The Table: As chips and systems become more complicated, more verification tasks get abstracted. So do we need more specialists who are experts in specific tasks, or do we need more generalists who know how to use the tools but don't necessarily have the depth of understanding? Or do we need some way to balance both? Semiconductor Engineering sat down with a panel of experts, includi... » read more

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