tag: Synopsys

Panel-Level Packaging’s Second Wave Meets Engineering Reality
By Gregory Haley - 16 Apr, 2026 - Comments: 0

Key Takeaways Panel-level packaging is arriving not because the engineering is ready, but because wafer-level economics are breaking down. Glass improves the warpage and dimensional stability problems of organic substrates but introduces a different class of failure modes that require materials solutions, not process adjustments. The central challenges of panel-level processing are m... » read more

Chiplet Standards Aim For Plug-n-Play
By Bryon Moyer - 16 Apr, 2026 - Comments: 0

Key Takeaways Die-to-die chiplet standards are only the beginning. Many more standards are necessary for a chiplet marketplace. A number of such standards have either had initial versions released or are in progress. Existing work covers packaging, a system architecture, various design kits, a universal link layer, and updates to BoW. Today’s chiplets exist in silos. In a ... » read more

Automate And Speed Up TCAD Calibration With Expert Modules And ML Calibration Accelerator
By Saurabh Suryavanshi - 16 Apr, 2026 - Comments: 0

Increasing complexity in semiconductor manufacturing has pushed the time to market and R&D costs significantly higher. In the world of AI, there is increased focus on efficiency to help address these issues simultaneously. Wafer-based learning, which is an iterative and linear process, is a key contributor to the increased semiconductor development time and cost. Technology computer-aided d... » read more

Blog Review: Apr. 15
By Jesse Allen - 15 Apr, 2026 - Comments: 0

Cadence's Wilson Kobalkar shares why eUSB2‑V2 represents a major evolutionary step for the USB 2.0 ecosystem, including how it achieves multi‑gigabit HSx operation and why symmetric/asymmetric modes unlock new design possibilities. Synopsys' Akanksha Soni explains the difference between metal-oxide-metal, metal-insulator-metal, and metal-oxide-semiconductor capacitors, identifying the ad... » read more

AI Growing Impact On Chip Design And EDA Tools
By Ed Sperling - 15 Apr, 2026 - Comments: 0

Key Takeaways Many workflows in the data center are customer-specific, which is part of the reason there is so much interest in agentic AI-enabled tools. Large systems companies are pressing EDA vendors for performance improvements to keep pace with their AI workflows. The makeup of design teams is changing as AI infiltrates more of the chip design process. Experts at the Ta... » read more

Startup Funding: Q1 2026
By Jesse Allen - 13 Apr, 2026 - Comments: 0

The new year started off with a bang for private semiconductor companies, with 18 garnering mega funding rounds exceeding $100 million, and two, Rapidus and Cerebras, reaching the $1 billion mark. Predictably, the vast majority of those are either designing chips primarily for AI inference workloads or attempting to overcome bandwidth limitations by improving interconnects from the chip level t... » read more

Early HBM4 Validation Points The Way For Next Generation AI And HPC Systems
By Brett Murdock - 09 Apr, 2026 - Comments: 0

As AI and high‑performance computing systems continue to scale, memory bandwidth has emerged as a primary system‑level constraint. Larger models, higher compute density, and increasingly complex multi‑die designs are driving the need for memory interfaces that can deliver extreme bandwidth while operating within tight power and signal‑integrity margins. High‑Bandwidth Memory (HBM) has... » read more

DRAM’s Whac‑A‑Mole Security Crisis
By Bryon Moyer - 09 Apr, 2026 - Comments: 0

Key takeaways: Rowhammer remains a DRAM security threat, while Rowpress has increasingly become a related threat. New commands issued by the memory controller can help manage refreshes, but they’re not a perfect solution. A smaller, vertical DRAM cell may eliminate the problem, but it’s years away. Rowhammer has been a persistent DRAM issue across several memory generati... » read more

A New Era For Co-Processing
By Brian Bailey - 09 Apr, 2026 - Comments: 0

Key Takeaways: There is no single processor capable of executing everything efficiently, meaning that multiple processors are required. Maximum efficiency is gained by minimizing the movement of data. Architects must maximize efficiency for today's workloads, while also adding enough flexibility to handle tomorrow's. New processor architectures are rapidly evolving thanks to... » read more

Fast Isn’t Fast Enough: Redefining Metrics for Edge AI
By Ann Mutschler - 09 Apr, 2026 - Comments: 0

Key Takeaways: Edge AI performance is about low latency and power efficiency, not peak TOPS. Memory bandwidth and data movement now limit edge AI more than compute. Successful edge AI requires balanced hardware, software, and fast model updates. Experts At The Table: Today’s chip architect must contend with multiple factors when architecting AI processors for fast and effi... » read more

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