Blog Review: Apr. 15

Cadence’s Wilson Kobalkar shares why eUSB2‑V2 represents a major evolutionary step for the USB 2.0 ecosystem, including how it achieves multi‑gigabit HSx operation and why symmetric/asymmetric modes unlock new design possibilities.

Synopsys’ Akanksha Soni explains the difference between metal-oxide-metal, metal-insulator-metal, and metal-oxide-semiconductor capacitors, identifying the advantages, disadvantages, and key applications of each.

Siemens’ Spencer Acain and Russell Klein chat about the benefits of using HLS for developing highly customized AI chips and how applying specially trained AI early in the design process can predict many key characteristics of the final chip.

Intel Foundry’s Han Wui Then introduces an ultra-thin gallium nitride chiplet built on 300mm GaN-on-silicon wafers to combine GaN transistors with traditional silicon-based digital circuits on a single chip.

Keysight’s Amritam Putatunda explores the structure of AI prompts and whether they primarily rely on compute, memory, or latency resources changes how they interact with the design of inference infrastructure.

Arm’s Jade Alglave introduces a chatbot tool that aims to provide quick answers to complex questions about the Arm architecture.

SEMI’s Sarah Shen presents an overview of discussion topics at the latest Quality Benchmarking Consortium meeting.

Plus, check out the blogs featured in the latest Low Power-High Performance newsletter:

Rambus’ Lou Ternullo finds that careful coordination between PCIe 8.0 PHY and controller layers is needed as data rates continue to increase.

Quadric’s Steve Roddy provides a concrete example of how architectural boundaries influence system behavior.

Synopsys’ Brett Mudock finds that first silicon alone is no longer sufficient for establishing next-generation designs.

Expedera’s Sharad Chole contends that edge intelligence is hampered by underutilized compute and the solution is to think in terms of packets, not layers.

Siemens’ Sudarshan Deo digs into power delivery, now spanning stacked dies, interposers, bridges, and packages connected by thousands of micro-bumps and TSVs.

Arm’s Odin Shen outlines a complete pipeline that can run on a single workstation for training a humanoid robot to walk over rough terrain.

Cadence’s Tanushri Shah discusses validation of an optimized data movement architecture that ensures arithmetic units receive a steady stream of data every cycle.