tag: Synopsys

Replay‑based Validation as a Scalable Methodology for Chiplet‑based Systems (Intel, Synopsys)
By Technical Paper Link - 18 Mar, 2026 - Comments: 0

A new technical paper, "ODIN-Based CPU-GPU Architecture with Replay-Driven Simulation and Emulation," was published by researchers at Intel, Nvidia and Synopsys. Abstract "Integration of CPU and GPU technologies is a key enabler for modern AI and graphics workloads, combining control-oriented processing with massive parallel compute capability. As systems evolve toward chiplet-based archite... » read more

Blog Review: Mar. 18
By Jesse Allen - 18 Mar, 2026 - Comments: 0

Cadence's Jamdagni Trivedi explains the UALink Protocol Level Interface, which defines how devices exchange data and control information, and shares insights into its structure, functionality, and significance in multi-node accelerator systems. Synopsys' Dustin Todd argues that AI sovereignty will be defined by and built on strategic interdependence, where countries develop and retain meanin... » read more

AI Design Reshapes Data Management
By Ann Mutschler - 16 Mar, 2026 - Comments: 0

Key takeaways: Integrating AI into chip workflows is pushing companies to overhaul their data management strategies, shifting from passive storage to active, structured, and machine-readable systems. As training and inference workloads grow, data movement, congestion, and energy efficiency become the dominant challenges, often surpassing raw compute capability. Proprietary and comple... » read more

Chip Industry Week In Review
By The SE Staff - 13 Mar, 2026 - Comments: 0

Disruptions caused by the Iran conflict have taken about one third of the global helium supply off the market, an essential gas for semiconductor manufacturing, reports the World Economic Forum. Other potential impacts for the chip industry include bromine and other chemical shortages, logistical disruptions, and higher energy prices incurred by fabs in Asia. Top Deals IBM and Lam R... » read more

CPO Is Extending The Limits Of What’s Possible In AI Data Centers
By Ann Mutschler - 12 Mar, 2026 - Comments: 0

Key Takeaways I/O architecture must be co-designed with compute from day one. Partitioning SoCs into heterogeneous chiplets (compute, EIC, PIC, lasers) directly affects power delivery, floor-planning, interconnect topology, and system scalability. Successful CPO designs require architects to think in multi-physics terms, balancing electrical signaling, thermal stability, optical beha... » read more

AI Power on the Edge
By Brian Bailey - 12 Mar, 2026 - Comments: 0

Key takeaways Power and thermal become primary design considerations, not just optimizations. Hardware architectures need to be developed from the ground up. Hardware/software/model co-development is essential. Implementing AI on the edge is driven by a different set of metrics than training or even inference in the cloud. It makes power a first-class citizen, if not the mos... » read more

Scale Up, Scale Out Get a New Partner
By Bryon Moyer - 12 Mar, 2026 - Comments: 0

Key Takeaways: Three AI data center scaling strategies are scale-up, scale-out, and scale-across. Scale-up is within a rack; scale-out is between racks; scale-across is between data centers. Each of the three uses a different interconnect strategy to optimize either latency or jitter. As today’s data center workloads — especially for AI and HPC — outgrow the physical, ... » read more

Customizing Foundation IP For Ultra-Low-Voltage Designs
By Daryl Seitzer - 12 Mar, 2026 - Comments: 0

By Daryl Seitzer, Andrew Appleby, and Mohammad Tanveer Building a new system-on-chip (SoC) starts with assembling the right foundational elements—pre‑verified IP for logic, memory, I/O, and other essential functions. Standard IP solutions typically address most common design needs, but some projects call for more specialized approaches, especially when innovation is critical or when t... » read more

Enabling Seamless Monitoring, Test, And Repair In Multi-Die Designs
By Yervant Zorian - 10 Mar, 2026 - Comments: 0

By Yervant Zorian and Sandeep Kumar Goel Anyone who follows the semiconductor industry knows that the accelerating performance, scale and energy efficiency demands of the AI revolution are outpacing the advances achievable by simply pushing the chip performance of monolithic, single-die designs. Multi-die design using 2.5D and 3D technologies has emerged as a necessity to keep the pace of in... » read more

Detecting Chemical Variability At Advanced Nodes
By Gregory Haley - 10 Mar, 2026 - Comments: 2

Key Takeaways Yield loss is increasingly driven by molecular variability in thin films, interfaces, and contamination rather than visible defects. Reliability issues often appear first as parametric drift or margin erosion under workload and thermal stress. Detection requires correlating molecular metrology, embedded electrical telemetry, and AI-driven wafer inspection. As s... » read more

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