Week In Review: Design, Low Power


Micron acquired FWDNXT, an AI software and hardware startup. Founded in 2017 and based in Lafayette, Indiana, FWDNXT, specializes in building machine learning deep neural network inference accelerators scalable from edge devices to server-class performance as Xilinx FPGAs, SoCs, or SDK. The company's engine already powers Micron's Deep Learning Accelerator (DLA) technology. “FWDNXT is an a... » read more

Week in Review: IoT, Security, Autos


IoT/Edge Achronix teamed up with Bittware to develop a smart accelerator card based on a 7nm FPGA from Achronix. The card is targeted for edge devices, where pre-processing and acceleration of data movement is critical due to the enormous quantity of data being generated by sensors. The strategy is to move the processing closer to the data, rather than processing input from multiple sensors in... » read more

Tricky Tradeoffs For LPDDR5


LPDDR5 is slated as the next-gen memory for AI technology, autonomous driving, 5G networks, advanced displays, and leading-edge camera applications, and it is expected to compete with GDDR6 for these applications. But like all next-gen applications, balancing power, performance, and area concerns against new technology options is not straightforward. These are interesting times in the memory... » read more

Blog Review: Oct. 30


Cadence's Paul McLellan checks out the future of the automotive industry, the options for making the transition to autonomous driving, and how experience with electric vehicles influences perception of them. In a video, Mentor's Colin Walls digs into the challenges of testing memory in an embedded system. A Synopsys writer looks at doubling bandwidth in PCIe 5.0, the PHY logical changes a... » read more

Visually Assisted Layout In Custom Design


Avina Verma, group director for R&D in Synopsys’ Design Group, explains why visual feedback and graphical guidance are so critical in complex layouts, particularly for mixed-signal environments. » read more

Rapid Evolution For Verification Plans


Verification plans are rapidly evolving from mechanisms to track verification progress into multi-faceted coordination vehicles for several teams with disparate goals, using complex resource management spread across multiple abstractions and tools. New system demands from industries such as automotive are forcing tighter integration of those plans with requirements management and product lif... » read more

Week In Review: Design, Low Power


ANSYS will acquire Dynardo, a provider of simulation process integration and design optimization (PIDO) technology. Dynardo's tools include algorithms for optimization, uncertainty quantification, robustness, scenario variation, sensitivity analysis, simulation workflow building and data mining. Based in Weimar, Germany, Dynardo was founded in 2001 and has been an ANSYS software partner; the ac... » read more

Week in Review: IoT, Security, Autos


Products/Services Rambus reports completing the sale of its Payments and Ticketing businesses to Visa for $75 million in cash. “With 30 years of experience pushing the envelope in semiconductor design, we look toward a future of continued innovation to carry on our mission of making data faster and safer,” Rambus President and CEO Luc Seraphin said in a statement. “Completing this transa... » read more

Functional Safety Implementation Goes Mainstream


Electronics engineers are being thrust into the automotive market like never before. The move to electrify automobiles, along with the advent of self-driving cars, means that silicon designers will be designing ever more sophisticated automotive ICs. But cars aren’t like most other electronic systems; it’s imperative that they cause no harm should they fail. This brings us to the realm o... » read more

IP Management And Development At 5/3nm


The growing complexity of moving to new process nodes is making it much more difficult to create, manage and re-use IP. There are more rules, more data to manage, and more potential interactions as density increases, both in planar implementations and in advanced packaging. And the problems only get worse as designs move to 5nm and 3nm, and as more heterogeneous components such as accelerato... » read more

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