Week in Review – IoT, Security, Autos


Products/Services Cadence Design Systems is working with Adesto Technologies to grow the Expanded Serial Peripheral Interface (xSPI) communication protocol ecosystem, for use in Internet of Things devices. The Cadence Memory Model for xSPI allows customers to ensure optimal use of the octal NOR flash with the host processor in an xSPI system, including support for Adesto’s EcoXiP octal xSPI ... » read more

Why EV Battery Design Is So Difficult


Automotive batteries always have been treated as plug-and-play parts of a vehicle, but that approach no longer works in electric vehicles. In fact, the battery is now a differentiating factor, and it is the heaviest and most expensive component. What used to be a relatively simple component has been replaced by a variety of sensors to measure complex static thermal and aging effects, as well... » read more

New Security Risks Create Need For Stealthy Chips


Semiconductors are becoming more vulnerable to attacks at each new process node due to thinner materials used to make these devices, as well as advances in equipment used to simulate how those chips behave. Thinner chips are now emitting light, electromagnetic radiation and various other types of noise, which can be observed using infrared and acoustic sensors. In addition, more powerful too... » read more

ML, Edge Drive IP To Outperform Broader Chip Market


The market for third-party semiconductor IP is surging, spurred by the need for more specific capabilities across a wide variety of markets. While the IP industry is not immune to steep market declines in semiconductor industry, it does have more built-in resilience than other parts of the industry. Case in point: The top 15 semiconductor suppliers were hit with an 18% decline in 2019 first-... » read more

New Vision Technologies For Real-World Applications


Computer vision – the ability of a machine to ‘infer’ or extract useful information from a two-dimensional image or an uncompressed video stream of images – has the ability to change our lives. It can enable self-driving cars, empower robots or drones to see their way to delivering packages to your doorstep, and can turn your face into a payment method (Figure 1). To achieve these advan... » read more

Blog Review: Oct. 2


In a video, Cadence's Tom Hackett explains finite element analysis by looking at a simple model of a bridge and showing why FEA techniques are required for analysis of real-world structures. Synopsys' Taylor Armerding examines why the 156-year-old False Claims Act has new relevance when companies are accused of failing to meet cybersecurity standards. Mentor's Colin Walls demystifies memo... » read more

Configure, Confirm, Ship: Build Secure Processor-Based Systems with Faster Time-to-Market


Security is a first-order design requirement for processor-based systems. Processor designers implement security functionality directly into the hardware itself to protect the system at its most fundamental layer. System integrators that use processor IP such as Synopsys’ DesignWare ARC processors must ensure that they configure and manage the protection and security features correctly, and t... » read more

Security Tradeoffs In A Shifting Global Supply Chain


Experts at the Table: Semiconductor Engineering sat down to discuss a wide range of hardware security issues and possible solutions with Norman Chang, chief technologist for the Semiconductor Business Unit at ANSYS; Helena Handschuh, fellow at Rambus, and Mike Borza, principal security technologist at Synopsys. What follows are excerpts of that conversation. The first part of this discussion ca... » read more

Week in Review – IoT, Security, Autos


Products/Services Achronix Semiconductor joined Taiwan Semiconductor Manufacturing’s IP Alliance Program, part of the foundry’s Open Innovation Platform. Achronix’s Speedcore eFPGA IP is available today on TSMC 16nm FinFET Plus (16FF+) and N7 process technologies, and it will be soon available on TSMC 12nm FinFET Compact Technology (12FFC). Cadence Design Systems announced that its di... » read more

Week In Review: Design, Low Power


eSilicon debuted its 7nm high-bandwidth interconnect (HBI)+ PHY IP, a special-purpose hard IP block that offers a high-bandwidth, low-power and low-latency wide-parallel, clock-forwarded PHY interface for 2.5D applications such as chiplets. HBI+ PHY delivers a data rate of up to 4.0Gbps per pin. Flexible configurations include up to 80 receive and 80 transmit connections per channel and up to 2... » read more

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