tag: Synopsys

TCAD-Based AI Models For Modern Fab Workflows
By Saurabh Suryavanshi - 20 Mar, 2025 - Comments: 0

The relentless pace of semiconductor development continues unabated. Despite the slowdown in Moore’s law, feature sizes continue to shrink as new geometries come online. Constant innovations in both fab processes and device design offer new opportunities but present new challenges. As in so many other areas of electronics, artificial intelligence (AI) is starting to play a significant role. ... » read more

What Exactly Are Chiplets And Heterogeneous Integration?
By Bryon Moyer - 20 Mar, 2025 - Comments: 1

The terms “chiplet” and “heterogeneous integration” fill news pages, conference papers, and marketing presentations, and for the most part engineers understand what they're reading. But speakers sometimes stumble during a presentation trying to figure out whether a particular die qualifies as a chiplet, and heterogeneous integration comes in different guises for different people. Both t... » read more

Chip Failures: Prevention And Responses Over Time
By Ed Sperling - 19 Mar, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss the causes of chip failures, how to respond to them, and how that can change over time, with Steve Pateras, vice president of marketing and business development at Synopsys; Noam Brousard, vice president of solutions engineering at proteanTecs; Harry Foster, chief verification scientist at Siemens EDA; and Jerome Toublanc, hi... » read more

Blog Review: Mar. 19
By Jesse Allen - 19 Mar, 2025 - Comments: 0

Cadence's Neelabh Singh explains the defined port operations of USB4 that are used to bring transmitters burst and receivers of a design under test into compliance mode and to execute tests like bit error tests, error rate tests, clock switch tests, TxFFE equalization tests, and electrical idle tests. Siemens EDA's Stephen V. Chavez examines the use of blind and buried vias in high-density i... » read more

New Data Center Protocols Tackle AI
By Bryon Moyer - 17 Mar, 2025 - Comments: 0

Compute nodes in AI and HPC data centers increasingly need to reach out beyond the chip or package for additional resources to process growing workloads. They may commandeer other nodes in a rack (scale-up) or employ resources in other racks (scale-out). The problem is there currently is no open scale-up protocol. So far this task has been dominated by proprietary protocols, because much of ... » read more

Chip Industry Week In Review
By The SE Staff - 14 Mar, 2025 - Comments: 0

ASML and imec signed a five-year strategic partnership to advance semiconductor innovation and sustainable technology. The collaboration will leverage ASML’s full product portfolio, including high-NA EUV, DUV immersion, and advanced metrology tools, within imec’s pilot line for sub-2nm R&D. Supported by EU and national funding, it will also drive research in silicon photonics, memory, a... » read more

Easier Assertion Development And Debug With Simulation Replay
By Vin Liao - 13 Mar, 2025 - Comments: 0

By Vin Liao and Robert Ruiz Assertions and assertion IP (AIP) are a core part of the register transfer level (RTL) verification environment for all modern chip development projects. Assertions can be considered as statements of design intent, specifying how the design should behave—and not behave—under specified conditions. They range from simple statements, for example, that a multi-bit... » read more

Chiplets Add New Power Issues
By Ann Mutschler - 13 Mar, 2025 - Comments: 0

Delivering and managing power are becoming key challenges in the rollout of chiplets, adding significantly to design complexity and forcing chipmakers to weigh tradeoffs that can have a big impact on the performance, reliability, and the overall cost of semiconductors. Power is a concern for every chip and chiplet design, even if the specifics differ based on the application. Systems vendors... » read more

Integrating Data From Design, Manufacturing, And The Field
By Adam Kovac - 13 Mar, 2025 - Comments: 0

Chip design is starting to include more options to ensure chips behave reliably in the field, boosting the ability to tweak both hardware and software as chips age. The basic problem is that as dimensions become smaller, and as more features are added into devices — especially with heterogeneous assemblies of chiplets running some type of AI — the potential for thermally induced structur... » read more

LLE-Aware Design Methodology To Avoid Timing And Power Pessimism
By Synopsys - 12 Mar, 2025 - Comments: 0

As chips move to ever-finer geometries, the active region (diffusion) shapes of neighboring cells can impact timing analysis and power calculations for the entire design. The LLE (Local Layout Effect) impact must be measured, but the impact is reflected very conservatively using conventional approaches. This paper describes a LLE-aware design methodology that mitigates the conservatism of co... » read more

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