tag: SystemVerilog

Poised For Aspect-Oriented Design?
By Brian Bailey - 13 Aug, 2015 - Comments: 8

In 1992, [getperson id=" 11046 " comment="Yoav Hollander"] had the idea to take a software programming discipline called aspect-oriented programming (AOP) and apply it to the verification of hardware. Those concepts were incorporated into the [gettech id="31021" t_name="e"] language and [getentity id="22068" e_name="Verisity"] was formed to commercialize it. Hollander had seen that using obj... » read more

UVM: What’s Stopping You?
By Doug Amos - 02 Jul, 2015 - Comments: 0

These days, verification of the most complex designs is performed using a standard verification methodology, probably SystemVerilog-based [gettech id="31055" comment="UVM"]. Many verification teams have ramped up on UVM, but others have yet to take the plunge. Why is that? And how big a “plunge” is it, anyway? If UVM is as great as all that, then why hasn’t everybody adopted it already... » read more

More Data, Different Approaches
By Ed Sperling - 25 Jun, 2015 - Comments: 0

Scaling, rising complexity, and integration are all contributing to an explosion in data, from initial design to physical layout to verification and into the manufacturing phase. Now the question is what to do with all of that data. For SoC designs, that data is critical for identifying real and potential problems. It also allows verification engineers working the back end of the design flow... » read more

Tech Talk: Better Coverage
By Ed Sperling - 08 Apr, 2015 - Comments: 1

Atrenta's Yuan Lu talks about code coverage, functional coverage and the use of assertions in debugging designs. [youtube vid=Hpm-l1z8HTo] » read more

An Update On The IEEE 1801-2013 Unified Power Format Standard
By Barry Pangrle - 09 Feb, 2015 - Comments: 0

It’s been almost six years since the first IEEE 1801 standard was officially published in March of 2009, but the standard can trace its roots back to years before that date. On May 30, 2013 the IEEE released a press announcement for the most recent version of the standard, IEEE 1801-2013 (a.k.a. UPF 2.1). This brought forward a standard for the industry that is finally backed by all of the ma... » read more

Hybrid Verification: The Only Way Forward
By Brian Bailey - 01 Dec, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the state of the industry for [getkc id="10" kc_name=" functional verification"]. The inability of RTL [getkc id="11" kc_name="simulation"] to keep up with verification needs is causing rapid change in the industry. Taking part in the discussion are Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphics"]; Janick Bergeron, fe... » read more

Virtual Prototyping Takes Off
By Ed Sperling - 06 Nov, 2014 - Comments: 0

Semiconductor Engineering sat down with Barry Spotts, senior core competency FAE for fabric and tools at [getentity id="22186" comment="ARM"]; Vasan Karighattam, senior director of architecture for SoC and SSW engineering at [getentity id="22664" e_name="Open-Silicon"]; Tom De Schutter, senior product marketing manager for Virtualizer Solutions at [getentity id="22035" e_name="Synopsys"]; Larry... » read more

The Assertion Conundrum
By Ann Mutschler - 22 May, 2014 - Comments: 2

It is well documented and widely agreed that assertions can provide a tremendous benefit to design and verification teams by reducing and even eliminating debug – but their use is still not ubiquitous. Part of the reason is that assertions cannot be picked up casually, noted David Larson, director of verification at [getentity id="22150" e_name="Synapse Design"]. “This is because asserti... » read more

High Level Synthesis Grows Up
By Brian Bailey - 13 Mar, 2014 - Comments: 2

When Semiconductor Engineering proposed this Experts At The Table discussion, which was held at the recently concluded DVCon, [getentity id="22032" e_name="Cadence"] had yet to express its intention to purchase [getentity id="22087" e_name="Forte"]. Little did we know that the stakes in the [gettech id="31015" comment="high-level synthesis"] (HLS) arena were being raised so high. Is this an in... » read more

The New Verification Landscape
By Ed Sperling - 27 Jun, 2013 - Comments: 0

By Ann Steffora Mutschler Verification technologies and tools have never been more sophisticated. But putting together a methodology is more than just putting tools together. It starts with trying to get a handle on the complexity, knowing what to test, how to test and when. “UVM was standardized and people have been working to adopt that which has been generally a positive,” said Steve Ba... » read more

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