Chip Industry Technical Paper Roundup: Mar. 10


New technical papers recently added to Semiconductor Engineering’s library: [table id=412 /] Find more semiconductor research papers here. » read more

Field-Coupled Nanocomputing: Scalable And Efficient Post-Layout Optimization (TU Munich)


A new technical paper titled "Efficient and Scalable Post-Layout Optimization for Field-coupled Nanotechnologies" was published by researcher at the Technical University of Munich (TUM). Abstract "As conventional computing technologies approach their physical limits, the quest for increased computational power intensifies, heightening interest in post-CMOS technologies. Among these, Field... » read more

Chip Industry Week In Review


The 2024 IEEE International Electron Devices Meeting (IEDM) was held this week, prompting a number of announcements from: imec: Proposed a new CFET-based standard cell architecture for the A7 node containing two rows of CFETs with a shared signal routing wall in between, allowing standard cell heights to be reduced from 4 to 3.5T, compared to single-row CFETs. Integrated indium pho... » read more

Chip Industry Week In Review


The U.S. Department of Commerce and Amkor Technology signed a deal to provide up to $400 million in funding, under the CHIPS and Science Act, to build a previously announced end-to-end advanced packaging plant. The combined funding is expected to total about $2 billion. The new facility will add some 2,000 jobs in Peoria, Arizona. The SK hynix Board approved its Yongin Semiconductor Cluster... » read more

Chip Industry Technical Paper Roundup: June 18


New technical papers added to Semiconductor Engineering’s library this week. [table id=234 /] More ReadingTechnical Paper Library home » read more

Chip Industry Week In Review


Samsung unveiled its latest 2nm and 4nm process nodes, plus its AI solutions during the Samsung Foundry Forum. The company also introduced an aggressive roadmap for the next few years that includes 3D-ICs with logic-on-logic, starting in 2025; custom HBM with built-in logic; backside power delivery on 2nm technology in 2027; and co-packaged optics. In presentations at the event, the company als... » read more

Characterizing and Evaluating A Quantum Processor Unit In A HPC Center


A new technical paper titled "Calibration and Performance Evaluation of a Superconducting Quantum Processor in an HPC Center" was published by researchers at Leibniz Supercomputing Centre, IQM Quantum Computers, and Technical University of Munich. Abstract "As quantum computers mature, they migrate from laboratory environments to HPC centers. This movement enables large-scale deployments,... » read more

Chip Industry Technical Paper Roundup: Mar. 5


New technical papers added to Semiconductor Engineering’s library this week. [table id=201 /] » read more

Ultra-Low Power CiM Design For Practical Edge Scenarios


A technical paper titled “Low Power and Temperature-Resilient Compute-In-Memory Based on Subthreshold-FeFET” was published by researchers at Zhejiang University, University of Notre Dame, Technical University of Munich, Munich Institute of Robotics and Machine Intelligence, and the Laboratory of Collaborative Sensing and Autonomous Unmanned Systems of Zhejiang Province. Abstract: "Compute... » read more

Research Bits: November 6


Fast superatomic semiconductor Researchers from Columbia University created a fast and efficient superatomic semiconductor material based on rhenium called Re6Se8Cl2. Rather than scattering when they come into contact with phonons, excitons in Re6Se8Cl2 bind with phonons to create new quasiparticles called acoustic exciton-polarons. Although polarons are found in many materials, those in Re6Se... » read more

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