tag: test

Improving Test Coverage And Eliminating Test Ecapes Using Analog Defect Analysis
By Cadence - 06 May, 2020 - Comments: 0

While the analog and mixed-signal components are the leading source of test escapes that result in field failures, the lack of tools to analyze the test coverage during design has made it difficult for designers to address the issue. In this white paper, we explore the methodology for performing analog fault simulation of test coverage based on defect-oriented testing. In addition, we look at h... » read more

Redefining Device Failures
By Ed Sperling - 07 Apr, 2020 - Comments: 0

Can a 5nm or 3nm chip really perform to spec over a couple decades? The answer is yes, but not using traditional approaches for designing, manufacturing or testing those chips. At the next few process nodes, all the workarounds and solutions that have been developed since 45nm don't necessarily apply. In the early finFET processes, for example, the new transistor structure provided a huge im... » read more

Reliability Challenges Grow For 5/3nm
By Ed Sperling And Susan Rambo - 07 Apr, 2020 - Comments: 0

Ensuring that chips will be reliable at 5nm and 3nm is becoming more difficult due to the introduction of new materials, new transistor structures, and the projected use of these chips in safety- and mission-critical applications. Each of these elements adds its own set of challenges, but they are being compounded by the fact that many of these chips will end up in advanced packages or modul... » read more

The Story Behind Advanced Packaging, Heterogeneous Integration and Test
By FormFactor - 06 Apr, 2020 - Comments: 0

The introduction of AMD’S FIJI chip a few years ago marked an important technology turning point for the semiconductor industry. This revolutionary graphics product delivered capability and innovation by relying on the first commercial example of 2.5D heterogenous integration, featuring a GPU assembled with High-Bandwidth-Memory (HBM) using Through-Silicon-Via (TSV) interconnect and interpose... » read more

Test Is Becoming A Horizontal Process
By Ed Sperling - 10 Mar, 2020 - Comments: 3

Semiconductor test, once a discrete part of a well-orchestrated series of manufacturing steps, is looking more like a process that extends from the early concept stage in design to the end of life of whatever system that chip ultimately is used for. This has important ramifications for safety-critical markets in general, and the semiconductor industry in particular. Both worlds have been inc... » read more

Test Costs Spiking
By Ed Sperling - 10 Mar, 2020 - Comments: 1

The cost of test is rising as a percentage of manufacturing costs, fueled by concerns about reliability of advanced-node designs in cars and data centers, as well as extended lifetimes for chips in those and other markets. For decades, test was limited to a flat 2% of total manufacturing cost, a formula developed prior to the turn of the Millennium after chipmakers and foundries saw the traj... » read more

AI Chip DFT Techniques For Aggressive Time-To-Market
By Mentor, a Siemens Business - 10 Mar, 2020 - Comments: 0

AI chips have aggressive time-to-market goals. Designers can shave significant time off of DFT and silicon bring up using the techniques described in this paper. Leading AI semiconductor companies have already had success with Tessent DFT tools. To read more, click here. » read more

Brighter Future For Photonics
By Brian Bailey - 13 Feb, 2020 - Comments: 3

Photons increasingly are taking over where electrons are failing in communications, but mixing the two never has been easy. There always have been two potential implementation paths — building each on its own substrate and then stacking them, or building them on a single substrate. The tradeoff between the two solutions is more complex than it may initially appear, and ongoing improvements... » read more

Optimal End-to-End DFT Automation With Tessent Connect
By Mentor, a Siemens Business - 11 Feb, 2020 - Comments: 0

With the growth in design size and complexity, DFT engineers began adopting new methods to reduce DFT implementation time, reduce test costs, and reduce risks to design schedules by removing DFT from the critical path to tapeout. The primary method to accomplish large improvements to DFT efficiency is through a divide-and-conquer approach supported by Tessent’s RTL-based, hierarchical DFT ins... » read more

Ensuring Functional Safety In Design
By Ed Sperling - 05 Feb, 2020 - Comments: 0

Mohammed Abdelwahid (Ali), automotive logic test product manager at Mentor, a Siemens Business, discusses how to maximize coverage in the different ASIL standards for logic BiST, how to make testing more efficient, and what impact that has on area and test time. » read more

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