tag: test

The Single Best DFT Move You Can Make
By Jay Jahangiri - 08 Oct, 2019 - Comments: 0

A proven method to simplify a complex problem is to break it into smaller chunks. In the case of today’s large, complex SoCs, this means using hierarchical methods to design the blocks, then combine the results at the top level. While this sounds obvious, it hasn’t always been practical or technologically feasible to perform some tasks, like DFT, at the block level and translate that work s... » read more

From Womb To Tomb: A Lifetime Of Chip Data In A Common Language
By Noam Brousard - 08 Oct, 2019 - Comments: 0

Every integrated circuit (IC) has a lifetime of stories to tell. From design through the end of a chip’s life, it can let us know what’s happening all along the way, providing we give it a voice and the language to do so. But until we can gain access to this data, the lives of these ICs remain secret. In-chip monitoring opens up those secrets. It helps to optimize performance, and it is esp... » read more

The Unexpected Impact Of Lots On Hold
By Marie Ryan - 08 Oct, 2019 - Comments: 0

One of the biggest bottlenecks in any Subcon is Lots on Hold. The problem occurs many times a week on most factory floors. It’s something you’ve grown to loathe or endure. But, is there something you can do to reduce the amount of time lots spend on hold? In this article, we will explain what Lots on Hold are and how you can make the process less painful for your team and help improve on-ti... » read more

Testing Against Changing Standards In Automotive
By Ed Sperling and Kevin Fogarty - 08 Oct, 2019 - Comments: 0

The infusion of more semiconductor content into cars is raising the bar on reliability and changing the way chips are designed, verified and tested, but it also is raising a lot of questions about whether companies are on the right track at any point in time. Concerns about liability are rampant with autonomous and assisted driving, so standards are being rolled out well in advance of the te... » read more

Advanced Features Of High-Speed Digital I/O Devices: Data Delay
By NI - 07 Oct, 2019 - Comments: 0

In high speed digital communications, because of factors such as setup time and hold time, it might be important to delay the data from the edge of the clock. The different settings and parameters that affect data delay are discussed in this white paper. To read more, click here. » read more

Hierarchical DFT: Proven Divide-And-Conquer Solution Accelerates DFT Implementation And Reduces Test Costs
By Mentor, a Siemens Business - 07 Oct, 2019 - Comments: 0

Implementation of the most challenging DFT tasks is greatly simplified by the proven and widely-adopted automation available in Tessent products. This whitepaper describes the basic components of an RTL-based hierarchical DFT methodology, the benefits that it provides, and the tool automation that is available through Mentor’s Tessent products. The focus is on the techniques and automation of... » read more

New Challenges In Testing 5G Devices
By Ed Sperling - 07 Oct, 2019 - Comments: 0

Alejandro Buritica, senior solutions marketing manager at National Instruments, talks about what will be needed for mass-market testing of 5G devices, how to focus signals to overcome signal attenuation, and how to make over-the-air testing viable where leads are not exposed. » read more

The Growing Impact Of Portable Stimulus
By Brian Bailey - 26 Sep, 2019 - Comments: 0

It has been a year since Accellera's Portable Test and Stimulus Specification became a standard. Semiconductor Engineering sat down to discuss the impact it has had, and the future direction of it, with Dave Kelf, chief marketing officer for Breker Verification Systems; Larry Melling, product management director for Cadence; Tom Fitzpatrick, strategic verification architect for Mentor, a Siemen... » read more

Scan Compression Is No Longer About Compression
By Rohit Kapur - 16 Sep, 2019 - Comments: 0

Scan compression was introduced in the year 2000 and has seen rapid adoption. Nearly every design’s test methodology today implements this technology, which inserts compression logic in the scan path between the scan I/Os and the internal chains. In this article, we take a critical look at the technology to understand how scan compression has matured. The road to scan compression Since th... » read more

Test On New Technology’s Frontiers
By Ed Sperling And Susan Rambo - 10 Sep, 2019 - Comments: 2

Semiconductor testing is getting more complicated, more time-consuming, and increasingly it requires new approaches that have not been fully proven because the technologies they are addressing are so new. Several significant shifts are underway that make achieving full test coverage much more difficult and confidence in the outcome less certain. Among them: Devices are more connected an... » read more

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