tag: test

Tessent Cell-Aware Test
By Mentor, a Siemens Business - 10 Sep, 2018 - Comments: 0

Tessent Cell-Aware ATPG is a transistor-level ATPG-based test methodology that achieves significant quality and efficiency improvements by directly targeting specific shorts; opens and transistor defects internal to each standard cell; resulting in significant reductions in defect (DPM) levels. Traditional scan patterns are created using fault models that are based on the logical operation of t... » read more

Digital IC Bring-Up With A Bench-Top Environment
By Matthew Knowles - 23 Aug, 2018 - Comments: 0

One of the hottest markets for IC today is artificial intelligence (AI). The designs for AI chips are also among the largest and most complex, with billions of transistors, thousands of memory instances, and complex design-for-test (DFT) implementations with unique bring up and debug requirements. At this point, the volume of new AI chips is relatively low, but time-to-market is of paramount im... » read more

Accelerating Test Pattern Bring-Up For Rapid First Silicon Debug
By Mentor, a Siemens Business - 22 Aug, 2018 - Comments: 0

Reducing the time spent on silicon bring-up is critical in getting ICs into the hands of customers and staying competitive. Typically, the silicon bring-up process involves converting the test patterns to a tester-specific format and generating a test program that is executed by Automatic Test Equipment (ATE). This standard silicon bring-up flow is becoming too slow and expensive, especially fo... » read more

Changing The Design Flow
By Ed Sperling - 07 Aug, 2018 - Comments: 0

Synopsys’ Michael Jackson talks with Semiconductor Engineering about why it’s becoming necessary to fuse together various pieces of digital design. https://youtu.be/AOWh4wjw-ps » read more

Who’s Paying For Auto Chip Test?
By Ed Sperling - 06 Aug, 2018 - Comments: 0

Testing of automotive chips is becoming more difficult and time-consuming, and the problem is only going to get worse. There is more to this than simply developing new test equipment or devising a better design for test flow. There are multiple issues at play here, and some of them are at odds with the others. First, no one has experience using advanced-node chips in extreme environments.... » read more

The Chiplet Race Begins
By Mark LaPedus - 06 Aug, 2018 - Comments: 1

Momentum is building for the development of advanced packages and systems using so-called chiplets, but the technology faces some challenges in the market. A group led by DARPA, as well as Marvell, zGlue and others are pursuing chiplet technology, which is a different way of integrating multiple dies in a package or system. In fact, the Defense Advanced Research Projects Agency (DARPA), part... » read more

Debug Issues Grow At New Nodes
By Ann Mutschler - 26 Jul, 2018 - Comments: 0

Debugging and testing chips is becoming more time-consuming, more complicated, and significantly more difficult at advanced nodes as well as in advanced packages. The main problem is that there are so many puzzle pieces, and so many different use cases and demands on those pieces, that it's difficult to keep track of all the changes and potential interactions. Some blocks are "on" sometimes,... » read more

Testing Cars In Context
By Ed Sperling - 12 Jul, 2018 - Comments: 0

The choices for companies developing systems or components that will work in autonomous vehicles is to road test them for millions of miles or to simulate them, or some combination of both. Simulation is much quicker, and it has worked well in the semiconductor world for decades. Simulating a chip or electronic system in context is hard enough. But simulating a system of systems in the real... » read more

Preparing For A 5G World
By Ed Sperling - 12 Jul, 2018 - Comments: 0

Semiconductor Engineering sat down to talk about challenges and progress in 5G with Yorgos Koutsoyannopoulos, president and CEO of Helic; Mike Fitton, senior director of strategic planning and business development at Achronix; Sarah Yost, senior product marketing manager at National Instruments; and Arvind Vel, director of product management at ANSYS. What follows are excerpts of that conversat... » read more

Security Holes In Machine Learning And AI
By Ed Sperling - 09 Jul, 2018 - Comments: 0

Machine learning and AI developers are starting to examine the integrity of training data, which in some cases will be used to train millions or even billions of devices. But this is the beginning of what will become a mammoth effort, because today no one is quite sure how that training data can be corrupted, or what to do about it if it is corrupted. Machine learning, deep learning and arti... » read more

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