Transistor-Level Defect Diagnosis

By Geir Eide - 22 Dec, 2016 - Comments: 0

Each new semiconductor process node represents exciting opportunities for suppliers of design, manufacturing, test, and failure analysis solutions. A new process means new challenges to solve, and hopefully more money to be made. On the flip side, whenever solutions that address these new challenges are presented, we seldom hear how useful these are to more mature process nodes. One technology ... » read more

Expose Transistor-Level Yield Limiters With Cell-Aware Diagnosis

By Mentor, a Siemens Business - 21 Dec, 2016 - Comments: 0

Cell-aware diagnosis is a new and effective method to perform transistor-level diagnosis to identify defects inside standard cells. It leverages fault models derived from analog simulation and uses a fail data collection and diagnosis flow identical to that of traditional diagnosis. Cell-aware diagnosis in Tessent Diagnosis is the result of over 10 years of research in cell-aware test and was d... » read more

When Exposed To IoT, Big Iron ATE Will Rust

By NI - 14 Dec, 2016 - Comments: 0

When the first “smart” refrigerators were released in the early 2000s, consumers weren’t sure what to do with them. When Nest released the smart thermostat, though, a revolution happened. Humans were taken out of the loop because the thermostat learned on its own about desired temperature and how quickly it could cool or heat a house. And it could synchronize all of this better than a hum... » read more

Formal’s Roadmap

By Brian Bailey - 30 Nov, 2016 - Comments: 0

Formal verification has come a long way in the past five years as it focused on narrow tasks within the verification flow. Semiconductor Engineering sat down to discuss that progress, and the future of formal technologies, with [getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"]; Harry Foster, chief verification scientist at [g... » read more

Testing the Big Bang of Smart Devices

By NI - 19 Oct, 2016 - Comments: 0

Thanks to the proliferation of smart devices in the Internet of Things (IoT), it’s a circumstance not unlike the overwhelming sense of wonder and bewilderment that ancient Greek astronomer Ptolemy must have felt when gazing up at a sky full of stars on a clear winter’s night, trying to rationalize the vast tableau before him. But just as we wouldn’t critique early astronomers and philo... » read more

Transforming Testing Through Automation

By Synopsys - 12 Oct, 2016 - Comments: 0

"Test your code as you write it.” That’s a common mantra heard in many development teams today. However, for too many, that practice remains a lofty goal as opposed to a business reality. They lack the appropriate metrics and processes to make and measure progress and often underestimate the effort required to manage the cultural change. In this paper you will learn how Coverity: Red... » read more

Moving Automotive Test Into The Analog Domain

By Steve Pateras - 29 Sep, 2016 - Comments: 0

The amount of electronic content in passenger cars continues to grow rapidly, driven mainly by the integration of various advanced safety features. The industry’s move towards fully autonomous vehicles promises to even further increase the number of these safety features and consequentially, the electronic content required in each vehicle. Recent reports indicate that hundreds of semicondu... » read more

Analog Fault Simulation Challenges And Solutions

By Mentor, a Siemens Business - 28 Sep, 2016 - Comments: 0

The test time for digital circuit blocks in ICs has greatly decreased in the last 20 years, thanks to scan-based design-for-test (DFT), automatic test pattern generation (ATPG) tools, and scan compression. These technologies have greatly reduced the number of test vectors applied by automatic test equipment (ATE) while maximizing the coverage of a wide range of defect types. But for analog c... » read more

Accelerate Time To Market With Change Impact Testing

By Synopsys - 07 Sep, 2016 - Comments: 0

QA teams don’t have time to test everything yet they can’t afford to ship buggy code. Teams waste precious resources on tests that have no relevance to the changes that were made to the application. And worse, there may be holes in the testing coverage which could lead to regression risk. Learn how Coverity can help organizations shrink their testing cycles and reduce regression risk by foc... » read more

Putting Design Back Into DFT

By Brian Bailey - 25 Aug, 2016 - Comments: 0

Test always has been a delicate balance between cost and quality, but there are several changes happening in the industry that might cause a significant alteration in strategy. Part one of this two part series about [getkc id="47" comment="Design for Test (DFT)"] looked at changes in areas such as automotive, where built in self-test is becoming a mandated part of the design process. This co... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?