tag: testbench

LLM-Assisted Generation Of Formal Verification Testbenches: RTL to SVA (Princeton)
By Technical Paper Link - 28 Sep, 2023 - Comments: 0

A technical paper titled “From RTL to SVA: LLM-assisted generation of Formal Verification Testbenches” was published by researchers at Princeton University. Abstract: "Formal property verification (FPV) has existed for decades and has been shown to be effective at finding intricate RTL bugs. However, formal properties, such as those written as System Verilog Assertions (SVA), are time-con... » read more

Formal Verification Best Practices: Investigating A Deadlock
By Laurent Arditi - 28 Sep, 2023 - Comments: 0

To ensure a design is deadlock free with formal verification, one approach consists in verifying that it is “always eventually” able to respond to a request. The wording is important. Regardless of the current state and the number of cycles we must wait, in the future the design must respond. This translates very nicely using a type of SystemVerilog Assertion called “liveness propertie... » read more

Extending The Benefits Of UVM To Include AMS: An Update On Accellera’s UVM-AMS Standard Development
By Tom Fitzpatrick - 04 Oct, 2022 - Comments: 0

By Tom Fitzpatrick and Peter Grove SoC teams can be divided up into design and verification groups. For digital designs, the Universal Verification Methodology (UVM), initially developed by Accellera and now standardized as IEEE 1800.2, has been the industry standard for the past decade. Since most SoC designs also have analog and mixed-signal IP blocks, it would be ideal for verification en... » read more

Measuring The Complexity Of Processor Bugs To Improve Testbench Quality
By Philippe Luc - 28 Apr, 2022 - Comments: 0

I am often asked the question “When is the processor verification done?” or in other words “how do I measure the efficiency of my testbench and how can I be confident in the quality of the verification?” There is no easy answer. There are several common indicators used in the industry such as coverage and bug curve. While they are absolutely necessary, these are not enough to reach the ... » read more

Comparing And Spotting The Difference Between Two Simulations
By Vtool - 26 Jan, 2022 - Comments: 0

Comparing is a basic skill we all use in our daily lives in order to understand reality and analyze situations. When it comes to chip verification, the fundamental task of checking also involves comparing because checking is always "checking vs. something" — the ASIC specification and/or a model. In practice, when we encounter a failing test, oftentimes we have a comparable passing tes... » read more

Four Requirements To Improve Chip Design Debug
By Taruna Reddy - 26 Aug, 2021 - Comments: 0

Debug has always been a painful and unavoidable part of semiconductor design and, despite many technological advances, it remains one of the dominant tasks in chip development. At one time, most bugs were detected and diagnosed on actual devices in the bring-up lab, where both visibility and controllability are severely limited. It is certainly true that debugging the results from pre-silicon t... » read more

Adding Value To Open-Source RISC-V Cores With Verification
By Lee Moore - 22 Apr, 2021 - Comments: 0

By Steve Richmond (Silicon Labs), Mike Thompson (OpenHW Group), and Lee Moore (Imperas Software) Modern SoC verification has matured to the point that some are suggesting the use of the word ‘prototype’ when referring to the first silicon samples is now unnecessary. This is due in part to the commercial EDA industry, which has provided the innovation and tools used throughout the design... » read more

Verification Convergence: Problem Definition
By Hagai Arbel - 30 Nov, 2020 - Comments: 0

A while ago, I had to go to the ER with my friend who suddenly had a numb feeling in his face. He felt okay (and everything else is okay with him), but better be safe than sorry. While the doctor examined him I noticed that before tracing the problem itself, she asked some questions to rule-out a problem she was already familiar with and that can manifest itself in similar ways. Only then, a... » read more

I’m Almost Done
By Hagai Arbel - 12 Oct, 2020 - Comments: 0

The city of Belgrade is renovating the street where I live. They are also building a new building next to mine so that I can see the construction work from my balcony. Last week, they blocked the street for some 20 minutes, and people got out of their cars and waited outside for the road to open. The construction workers were not in a hurry, and it seemed like everyone was ok with that, so I... » read more

Confusion Persists In Verification Terms
By Brian Bailey - 27 Aug, 2020 - Comments: 7

I find it amazing that an area of technology that attempts to show, beyond a reasonable doubt, that a design will work before it is constructed can be so bad at getting some basic things right. I am talking about verification terminology. I have been in this industry for over 40 years and it is not improving. In fact, it is getting worse. The number of calls I have with people where they hav... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy