tag: thermal

The 3D-IC Multiphysics Challenge Dictates A Shift-Left Strategy
By John Ferguson - 25 Apr, 2024 - Comments: 0

As the industry marches forward in a 3D-IC centric design approach (figure 1), we are facing a new problem. Sometimes referred to as “electro-thermal” or “electro-thermo-mechanical,” it really is the confluence of multiple forms of physics exerting impacts on both the physical manufacture and structure of these multi-die designs and their electrical behavior. Fig. 1: Illustration... » read more

Package Integrated Vapor Chamber Heat Spreaders
By Sanghyuk Kim - 21 Mar, 2024 - Comments: 0

With continuous increases in computational demand in nearly all electronics market segments, even historically lower power packaging is being driven into challenging thermal management situations. Node shrink alone is reaching a limit in maintaining track with Moore’s law. The economics and yield challenges of large monolithic system on chip (SoC) designs are driving the development of silico... » read more

3D-IC Intensifies Demand For Multi-Physics Simulation
By Ann Mutschler - 20 Mar, 2024 - Comments: 0

The introduction of full 3D-ICs will require a simultaneous analysis of various physical effects under different workloads, a step-function change that will add complexity at every step of the design flow, expand and alter job responsibilities, and bring together the analog and digital design worlds in unprecedented ways. 3D-ICs will be the highest-performance advanced packaging option, in s... » read more

Predicting Warpage in Different Types of IC Stacks At Early Stage Of Package Design
By Technical Paper Link - 15 Mar, 2024 - Comments: 0

A new technical paper titled "Warpage Study by Employing an Advanced Simulation Methodology for Assessing Chip Package Interaction Effects" was published by researchers at Siemens EDA, D2S, and Univ. Grenoble Alpes, CEA, Leti. Abstract: "A physics-based multi-scale simulation methodology that analyses die stress variations generated by package fabrication is employed for warpage study. The ... » read more

Backside Power Delivery Adds New Thermal Concerns
By Karen Heyman - 14 Mar, 2024 - Comments: 0

As the semiconductor industry gears up for backside power delivery at the 2nm node, implementation of the technology requires a re-thinking of established design practices. While some EDA tools are already qualified, designers must acquaint themselves with new issues, including making place-and-route more thermal-aware and how to manage heat dissipation with less shielding and thinner substr... » read more

Can Data Centers Afford To Turn Up The Heat?
By Mark Seymour - 25 Jan, 2024 - Comments: 0

Typically, when we discuss digital twin software for data centers, we highlight how engineers can use data center software to model complex thermals using physics-based simulation and find effective ways to cool IT equipment. However, there are compelling efficiency and cost-saving reasons for data center operators to actively seek to run their data centers hotter. But how can this be done wit... » read more

Research Bits: Jan. 16
By Jesse Allen - 16 Jan, 2024 - Comments: 0

3D stacking of 2D materials Researchers from Penn State University demonstrated monolithic 3D integration with 2D transistors made from 2D semiconductors called transition metal dichalcogenides. The 2D materials have unique electronic and optical properties, including sensitivity to light, making them ideal for use as sensors. “One challenge is the process temperature ceiling of 450 degre... » read more

Multi-Chiplet Marvels: Exploring Chip-Centric Thermal Analysis
By Louis Tsai - 11 Jan, 2024 - Comments: 0

The relationship between power consumption and thermal dynamics for chips is intricate. As power is consumed during the operation of a chip, it results in the generation of heat. This heat may dissipate from the device, metal routing, or the die itself, leading to increased temperatures on the chip. The dissipation process perpetually expends redundant energy, thereby compromising on the overal... » read more

Decoding GDS To Thermal Model Conversion
By Jasmine Jasmine - 14 Dec, 2023 - Comments: 0

Driven by Moore’s Law and modern, ubiquitous computation power demand, the market will continue to demand higher chip performance. Therefore, modern chips with ever-higher power densities present critical thermal challenges. With the ever-shrinking design margins, designers must manage their thermal budget at every stage of the design, from chip to system. Now, let us shift left and start ... » read more

Help, 3D-IC Is Stuck In A Country Song
By John Ferguson - 30 Nov, 2023 - Comments: 0

Every time I focus on three-dimensional (3D) integrated circuit (IC) design, I start hearing the Luke Bryan song “Rain Makes Corn, Corn Makes Whiskey.” Not because I need a strong drink to work with 3D-IC designs, but because there is a similar, although slightly more complicated, series of cause and effect issues that impact 3D-ICs. Pushing electrons through very thin metal wires and switc... » read more

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