Multi-Die Assemblies Complicate Parasitic Extraction


The shift from planar designs to multi-die assemblies with complex interconnects is transforming what had become almost an afterthought in the design process into a first-order challenge. Parasitics include things like inductance, capacitance, and resistance, which have become more problematic at advanced nodes due to increasing logic density, thinner interconnects and insulators, and a spik... » read more

A New RF Platform For Silicon MMIC And System Design


Next generation wireless modules combine innovative and proven RFIC/MMIC designs into a single package―delivering superior performance, lower power consumption, and reduced size, weight, and cost. Advanced system engineering plays a crucial role in this progress, with a strong focus on packaging interconnect design, RF analysis, and thermal and electromagnetic (EM) awareness that enable se... » read more

Thermal Analysis Of 3D Stacking And BEOL Technologies


Thermal challenges in 3D-IC designs can cause a significant risk in meeting performance specifications. While the pace of Moore’s Law has slowed in recent years, system technology co-optimization (STCO) promises to mitigate technology scaling bottlenecks with system architecture tuning based on emerging technology offerings, including 3D technology. AI-driven inference accelerators continu... » read more

Thermal-Aware DSE Framework for 3DICs, With Advanced Cooling Models


A new technical paper titled "Cool-3D: An End-to-End Thermal-Aware Framework for Early-Phase Design Space Exploration of Microfluidic-Cooled 3DICs" was published by researchers at University of Michigan, Shanghai Jiao Tong University and University of Virginia. Abstract "The rapid advancement of three-dimensional integrated circuits (3DICs) has heightened the need for early-phase design spa... » read more

Thermal Analysis Of 3D Stacking And BEOL Technologies With Functional Partitioning Of Many-Core RISC-V SoC


Thermal challenges in 3D-IC designs can cause a significant risk in meeting performance specifications. While the pace of Moore’s Law has slowed in recent years, system technology co-optimization (STCO) promises to mitigate technology scaling bottlenecks with system architecture tuning based on emerging technology offerings, including 3D technology. This white paper analyzes the impact of mat... » read more

Strain, Stress In Advanced Packages Drives New Design Approaches


Thermal and mechanical stresses are creating significant challenges in heterogeneous chiplet assemblies, increasing the time and cost required to work through all the possible physical effects, dependencies, and interactions, and driving demand for new tools. Unlike in the past, when various components were crammed into a planar SoC on a relatively thick substrate, the new substrates are bei... » read more

Ensure Reliability In Automotive ICs By Reducing Thermal Effects


In the relentless pursuit of performance and miniaturization, the semiconductor industry has increasingly turned to 3D integrated circuits (3D-ICs) as a cutting-edge solution. Stacking dies in a 3D assembly offers numerous benefits, including enhanced performance, reduced power consumption, and more efficient use of space. However, this advanced technology also introduces significant thermal di... » read more

New Approaches Needed For Power Management


Power is becoming a bigger concern as the amount of data being processed continues to grow, forcing chipmakers and systems companies to rethink compute architectures from the end point all the way to the data center. There is no simple fix to this problem. More data is being collected, moved, and processed, requiring more power at every step, and more attention to physical effects such as he... » read more

Architecting Chips For High-Performance Computing


The world’s leading hyperscaler cloud data center companies — Amazon, Google, Meta, Microsoft, Oracle, and Akamai — are launching heterogeneous, multi-core architectures specifically for the cloud, and the impact is being felt in high-performance CPU development across the chip industry. It's unlikely that any these chips will ever be sold commercially. They are optimized for specific ... » read more

What’s At Stake In System Design?


When engineers refer to system analysis, they are referring to tool functions for improving an overall electronics design. What you will gain from this eBook: Power and Signal Integrity Insights into harmonic balancing and crosstalk analysis Learning about loop gain and transmission rates Examining the necessity of power-aware systems Electromagnetic Analysis Knowledge ... » read more

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