tag: through-silicon vias

Changing Direction In Chip Design
By Ed Sperling - 26 Jan, 2017 - Comments: 1

Andrzej Strojwas, chief technologist at PDF Solutions and professor of electrical and computer engineering at Carnegie Mellon University—and the winner of this year's Phil Kaufman Award for distinguished contributions to EDA—sat down with Semiconductor Engineering to talk about device scaling, why the semiconductor industry will begin to fragment around new architectures and packaging, and ... » read more

Overcoming The Limits Of Scaling
By Ed Sperling - 29 Dec, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the increasing reliance on architectural choices for improvements in power, performance and area, with [getperson id="11425" comment=" Sundari Mitra"], CEO of [getentity id="22535" comment="NetSpeed Systems"]; Charlie Janac, chairman and CEO of [getentity id="22674" e_name="Arteris"]; [getperson id="11032" comment="Simon Davidmann"] CEO of [getentit... » read more

Stacked Die Changes
By Ed Sperling - 21 Sep, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; John Hunt, senior director of engineering at ASE; and Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. ... » read more

Stacked Die Changes
By Ed Sperling - 15 Sep, 2016 - Comments: 1

Semiconductor Engineering sat down to discuss advanced packaging with David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; John Hunt, senior director of engineering at ASE; and Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. ... » read more

Designing SoC Power Networks
By Brian Bailey - 11 Aug, 2016 - Comments: 0

Designing a power network for a complex SoC is becoming critical for the success of the product, but most chips are still using old techniques that are ill-suited to the latest fabrication technologies, resulting in an expensive, overdesigned product. Not only is the power network as designed too large, but this has several knock-on effects that impact area, timing and power. In the first pa... » read more

Advanced Packaging Options, Issues
By Ed Sperling - 23 Jun, 2016 - Comments: 0

Systems in package are heading for the mass market in applications that demand better performance and lower power. As they do, new options for cutting costs are being developed to broaden the appeal of this approach as an alternative to shrinking features. Cost has been one of the big deterrents for widespread adoption of [getkc id="82" kc_name="2.5D"]. Initially, the almost universal compla... » read more

Keeping The Whole Package Cool
By Katherine Derbyshire - 12 May, 2016 - Comments: 0

Heat dissipation is a critical issue for designers of complex chip-stacking and system-in-package devices. The amount of heat generated by a device increases as the number of transistors goes up, but the ability to dissipate the heat depends on the package surface area. Because the goal of 3D packaging is to squeeze more transistors into less overall space, new heat dissipation issues are em... » read more

2.5D Becomes A Reality
By Ed Sperling - 11 May, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss 2.5D and advanced packaging with Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; John Shin, vice president at [getentity id="22903" e_name="Marvell"]; Bill Isaacson, director of ASIC marketing at [getentity id="22242" e_name="eSilicon"]; Frank Ferro, senior di... » read more

2.5D Becomes A Reality
By Ed Sperling - 14 Apr, 2016 - Comments: 2

Semiconductor Engineering sat down to discuss 2.5D and advanced packaging with Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; John Shin, vice president at [getentity id="22903" e_name="Marvell"]; Bill Isaacson, director of ASIC marketing at [getentity id="22242" e_name="eSilicon"]; Frank Ferro, senior di... » read more

New Memory Approaches And Issues
By Ed Sperling - 14 Mar, 2016 - Comments: 1

New memory types and approaches are being developed and tested as DRAM and Moore's Law both run out of steam, adding greatly to the confusion of what comes next and how that will affect chip designs. What fits where in the memory hierarchy is becoming less clear as the semiconductor industry grapples with these changes. New architectures, such as [getkc id="202" kc_name="fan-outs"] and [getk... » read more

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