tag: timing closure

Three Ways To Speed Up Timing Closure Of High-Speed PCB Interfaces
By Cadence - 15 May, 2024 - Comments: 0

On advanced high-speed interfaces, timing closure can be an iterative process that can be time-consuming and frustrating. PCB designers need techniques and tools to make the process more efficient, so they can contribute to an overall faster time to market for the design. This article discusses three ways that the new Cadence Allegro TimingVision environment speeds up timing closure of high-spe... » read more

Golden Signoff ECO For Last-Mile Electronic Design Closure
By Manoj Chacko - 03 Oct, 2022 - Comments: 0

Electronic design developers really hate iterative, resource-intensive tasks that occur late in the project schedule. Most engineers are under tremendous time to market (TTM) pressure due to competition while being told that they must minimize the cost of both the project and the end chip. In addition, they are struggling to meet power, performance, and area (PPA) requirements far more aggressi... » read more

Challenges With Stacking Memory On Logic
By Ed Sperling - 22 Dec, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the changes in design tools and methodologies needed for 3D-ICs, with Sooyong Kim, director and product specialist for 3D-IC at Ansys; Kenneth Larsen, product marketing director at Synopsys; Tony Mastroianni, advanced packaging solutions director at Siemens EDA; and Vinay Patwardhan, product management group director at Cadence... » read more

ML-based Routing Congestion And Delay Estimation In Vivado ML Edition
By Xilinx - 03 Nov, 2021 - Comments: 0

The FPGA physical design flow offers a compelling opportunity for Machine Learning for CAD (MLCAD) for the following reasons: • An ML solution can be applied wholesale to a device family. • There is a vast data farm that can be harvested from device models and design data from broad applications. • There is a single streamlined design flow that an be instrumented, annotated, and quer... » read more

Using ML In EDA
By Ed Sperling - 20 Sep, 2021 - Comments: 0

Machine learning is becoming essential for designing chips due to the growing volume of data stemming from increasing density and complexity. Nick Ni, director of product marketing for AI at Xilinx, examines why machine learning is gaining traction at advanced nodes, where it’s being used today and how it will be used in the future, how quality of results compare with and without ML, and what... » read more

Lower Process Nodes Drive Timing Signoff Software Evolution
By Synopsys - 10 Nov, 2020 - Comments: 0

A dramatic rise in design complexity has led to a slew of new signoff challenges that impact the ability to predictably meet PPA targets. Smaller technology nodes and larger design sizes have caused the number of corners and modes to grow exponentially leading to much longer turnaround times for timing signoff. Moreover, larger design sizes demand huge compute resources for timing signoff. I... » read more

Lower Process Nodes Drive Timing Signoff Software Evolution
By Synopsys - 28 Oct, 2020 - Comments: 0

A dramatic rise in design complexity has led to a slew of new signoff challenges that impact the ability to predictably meet PPA targets. Smaller technology nodes and larger design sizes have caused the number of corners and modes to grow exponentially leading to much longer turnaround times for timing signoff. Moreover, larger design sizes demand huge compute resources for timing signoff. I... » read more

Early Verification Of Multi-Cycle Paths And False Paths In Simulation
By Synopsys - 09 Sep, 2020 - Comments: 0

Timing closure is a critical step in the chip development process. The performance and timing of a design must be verified, and any violations must be investigated and resolved. This includes the specification and verification of timing exceptions. This white paper focuses on false paths and multi-cycle paths, the use of Synopsys Design Constraints (SDC) to specify these exceptions, and the “... » read more

Distributed Design Implementation
By Ed Sperling - 04 Dec, 2019 - Comments: 0

PV Srinivas, group director for R&D at Synopsys, talks about the impact of larger chips and increasing complexity on design productivity, why divide-and-conquer doesn’t work so well anymore, and how to reduce the number of blocks that need to be considered to achieve faster timing closure and quicker time to market. » read more

Low Power Meets Variability At 7/5nm
By Ann Mutschler - 11 Apr, 2019 - Comments: 0

Power-related issues are beginning to clash with process variation at 7/5nm, making timing closure more difficult and resulting in re-spins caused by unexpected errors and poor functional yield. Variability is becoming particularly troublesome at advanced nodes, and there are multiple causes of that variability. One of the key ones is the manufacturing process, which can be affected by every... » read more

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