tag: Tokyo Electron

Week In Review: Manufacturing, Test
By Ed Sperling - 25 Mar, 2022 - Comments: 0

Worldwide fab equipment spending for front-end manufacturing is expected to hit $107 billion this year, an 18% year-over-year increase, according to SEMI’s latest World Fab Forecast report. “Crossing the $100 billion mark in spending on global fab equipment for the first time is a historic milestone for the semiconductor industry,” said Ajit Manocha, president and CEO of SEMI. Investme... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 30 Apr, 2021 - Comments: 0

Chipmakers and OEMs Intel wants $9.7 billion in subsidies for use in building a leading-edge fab in Europe, according to a report from Reuters. As reported, in March, Intel re-entered the foundry business, positioning itself against Samsung and TSMC at the leading edge, and against a multitude of foundries working at older nodes. Eighteen members of the European Union recently launched an ... » read more

Looming Issues And Tradeoffs For EUV
By Mark LaPedus - 25 Sep, 2017 - Comments: 5

Momentum is building for extreme ultraviolet (EUV) lithography, but there are still some major challenges to solve before this long-overdue technology can be used for mass production. [gettech id="31045" comment="EUV"] lithography—a next-generation technology that patterns tiny features on a chip—was supposed to move into production around 2012. But over the years, EUV has encountered se... » read more

Four Foundries Back MRAM
By Mark LaPedus - 23 Aug, 2017 - Comments: 4

Four major foundries plan to offer MRAM as an embedded memory solution by this year or next, setting the stage for what finally could prove to be a game-changer for this next-generation memory technology. GlobalFoundries, Samsung, TSMC and UMC plan to start offering spin-transfer torque magnetoresistive RAM (ST-MRAM or STT-MRAM) as an alternative or a replacement to NOR flash, possibly start... » read more

The 200mm Equipment Scramble
By Ed Sperling - 23 Aug, 2017 - Comments: 0

An explosion in 200mm demand has set off a frenzied search for used semiconductor manufacturing equipment that can be used at older process nodes. The problem is there is not enough used equipment available, and not all of the new or expanding 200mm fabs can afford to pay the premium for refurbished or new equipment. This may sound like a straightforward supply and demand issue, but behind t... » read more

Why Fabs Worry About Tool Parts
By Mark LaPedus - 17 Aug, 2017 - Comments: 2

Achieving high yields with acceptable costs is becoming much more difficult as chipmakers migrate to next-generation 3D NAND and finFET devices—but not just because of rising complexity or lithography issues. To fabricate an advanced logic chip, for example, a wafer moves from one piece of equipment to another in what amounts to 1,000 process steps or more in a fab. Any glitch with the equ... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 11 Aug, 2017 - Comments: 0

Fab tools Lam Research held an analyst event this week. The company indicated that the industry is in the midst of a memory boom, including both DRAM and 3D NAND. According to Amit Daryanani, an analyst with RBC, here was one of the big takeaways at the event: “The memory spend portion of WFE is more sustainable than previously assumed due to end-market drivers such as big data, automation, ... » read more

Electroplating IC Packages
By Mark LaPedus - 10 Apr, 2017 - Comments: 2

The electrochemical deposition (ECD) equipment market for IC packaging is heating up as 2.5D, 3D and fan-out technologies begin to ramp. [getentity id="22817" e_name="Applied Materials"]  recently rolled out an ECD system for IC packaging. In addition, Lam Research, TEL and others compete in the growing but competitive ECD equipment market for packaging. ECD—sometimes referred to as pl... » read more

Patterning Problems Pile Up
By Mark LaPedus - 20 Mar, 2017 - Comments: 4

Chipmakers are ramping up 16nm/14nm finFET processes, with 10nm and 7nm now moving into early production. But at 10nm and beyond, chipmakers are running into a new set of problems. While shrinking feature sizes of a device down to 10nm, 7nm, 5nm and perhaps beyond is possible using current and future fab equipment, there doesn't seem to be a simple way to solve the edge placement error (EPE)... » read more

BEOL Issues At 10nm And 7nm
By Ed Sperling - 31 Jan, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss problems with the back end of line at leading-edge nodes with Craig Child, senior manager and deputy director for [getentity id="22819" e_name="GlobalFoundries'"] advanced technology development integration unit; Paul Besser, senior technology director at [getentity id="22820" comment="Lam Research"]; David Fried, CTO at [getentity id="22210" e_name... » read more

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