tag: TSMC

Metrology Challenges For Gate-All-Around
By Mark LaPedus - 16 Apr, 2020 - Comments: 3

Metrology is proving to be a major challenge for those foundries working on processes for gate-all-around FETs at 3nm and beyond. Metrology is the art of measuring and characterizing structures in devices. Measuring and characterizing structures in devices has become more difficult and expensive at each new node, and the introduction of new types of transistors is making this even harder. Ev... » read more

Making Chips At 3nm And Beyond
By Mark LaPedus and Ed Sperling - 16 Apr, 2020 - Comments: 4

Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. The big question is what comes after that. Work is well underway for the 2nm node and beyond, but there are numerous challenges as well as some uncertainty on the horizon. There already are signs that the foundries have pushed out their 3nm production schedules by a few months due to various technical issu... » read more

Big Changes In Tiny Interconnects
By Ed Sperling - 16 Apr, 2020 - Comments: 1

One of the fundamental components of a semiconductor, the interconnect, is undergoing radical changes as chips scale below 7nm. Some of the most pronounced shifts are occurring at the lowest metal layers. As more and smaller transistors are packed onto a die, and as more data is processed and moved both on and off a chip or across a package, the materials used to make those interconnects, th... » read more

Designing Ultra Low Power AI Processors
By Ann Mutschler - 09 Apr, 2020 - Comments: 0

AI chip design is beginning to shift direction as more computing moves to the edge, adding a level of sophistication and functionality that typically was relegated to the cloud, but in a power envelope compatible with a battery. These changes leverage many existing tools, techniques and best practices for chip design. But they also are beginning to incorporate a variety of new approaches tha... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 27 Mar, 2020 - Comments: 0

Chipmakers TrendForce has released its projected foundry rankings in terms of sales for the first quarter. TSMC is still in first place, followed by Samsung, GlobalFoundries and UMC. Samsung has been ramping up chips based on its 7nm logic process using extreme ultraviolet (EUV) lithography. Now, Samsung is ramping up its DRAM devices using EUV and plans to expand its capacity in the arena.... » read more

Scaling Up Compute-In-Memory Accelerators
By Katherine Derbyshire - 19 Mar, 2020 - Comments: 3

Researchers are zeroing in on new architectures to boost performance by limiting the movement of data in a device, but this is proving to be much harder than it appears. The argument for memory-based computation is familiar by now. Many important computational workloads involve repetitive operations on large datasets. Moving data from memory to the processing unit and back — the so-called ... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 06 Mar, 2020 - Comments: 0

Fab tools, materials and packaging Intel has recognized 37 companies for its annual suppliers’ awards. The list includes equipment, materials, packaging houses and other segments. These suppliers have collaborated with Intel to implement process improvements with good products and services. See who made the list here. ---------------------------------------- Lam Research has introduced... » read more

3nm: Blurring Lines Between SoCs, PCBs And Packages
By Ann Mutschler - 02 Mar, 2020 - Comments: 5

Leading-edge chipmakers, foundries and EDA companies are pushing into 3nm and beyond, and they are encountering a long list of challenges that raise questions about whether the entire system needs to be shrunk onto a chip or into a package. For 7nm and 5nm, the problems are well understood. In fact, 5nm appears to be more of an evolution from 7nm than a major shift in direction. But at 3nm, ... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 28 Feb, 2020 - Comments: 2

SPIE At the SPIE Advanced Lithography conference, Lam Research has introduced a new dry resist technology for extreme ultraviolet (EUV) lithography. Dry resist technology is a new approach to deposit and develop EUV resists. It is a dry deposition technique with alternate compositions and mechanisms. By combining Lam’s deposition and etch process expertise with partnerships with ASML a... » read more

Week In Review: Design, Low Power
By Jesse Allen - 28 Feb, 2020 - Comments: 0

Tools Synopsys debuted the VC SpyGlass RTL Static Signoff platform featuring new noise reduction technology that uses machine learning to reduce noise by 10X without loss of quality of results. It also provides comprehensive CDC and RDC analysis to catch logic issues added during implementation, and is integrated with Synopsys' automated debug system. Ansys released RaptorH, a tool that com... » read more

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