tag: TU Munich

Characterizing and Evaluating A Quantum Processor Unit In A HPC Center
By Technical Paper Link - 10 Jun, 2024 - Comments: 0

A new technical paper titled "Calibration and Performance Evaluation of a Superconducting Quantum Processor in an HPC Center" was published by researchers at Leibniz Supercomputing Centre, IQM Quantum Computers, and Technical University of Munich. Abstract "As quantum computers mature, they migrate from laboratory environments to HPC centers. This movement enables large-scale deployments,... » read more

Chip Industry Technical Paper Roundup: April 23
By Linda Christensen - 23 Apr, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library. [table id=216 /] Find last week’s technical paper additions here. » read more

Comparison Of The Meta Modeling Approach With HGLs
By Technical Paper Link - 09 Apr, 2024 - Comments: 0

A new technical paper titled "The Argument for Meta-Modeling-Based Approaches to Hardware Generation Languages" was published by researchers at Infineon Technologies and TU Munich. Abstract "The rapid evolution of Integrated Circuit (IC) development necessitates innovative methodologies such as code generation to manage complexity and increase productivity. Using the right methodology for g... » read more

Chip Industry’s Technical Paper Roundup: May 23
By Linda Christensen - 23 May, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=104 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us... » read more

Non-Traditional Design of Dynamic Logic Gates and Circuits with FDSOI FETs
By Technical Paper Link - 19 May, 2023 - Comments: 0

A new technical paper titled "Non-Traditional Design of Dynamic Logics using FDSOI for Ultra-Efficient Computing" was published by researchers at University of Stuttgart, UC Berkeley, Indian Institute of Technology Kanpur, and TU Munich, with funding by the German Research Foundation. Abstract "In this paper, we propose a non-traditional design of dynamic logic circuits using Fully-Deplet... » read more

Chip Industry’s Technical Paper Roundup: Apr. 4
By Linda Christensen - 04 Apr, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=90 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us p... » read more

Covert Channel Between the CPU and An FPGA By Modulating The Usage of the Power Distribution Network
By Technical Paper Link - 30 Mar, 2023 - Comments: 0

A new technical paper titled "CPU to FPGA Power Covert Channel in FPGA-SoCs" was published by researchers at TU Munich and Fraunhofer Research Institution AISEC. Abstract: "FPGA-SoCs are a popular platform for accelerating a wide range of applications due to their performance and flexibility. From a security point of view, these systems have been shown to be vulnerable to various attacks... » read more

Chip Industry’s Technical Paper Roundup: Feb. 28
By Linda Christensen - 28 Feb, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=83 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us ... » read more

Security-Aware Compiler-Assisted Countermeasure to Mitigate Fault Attacks on RISC-V
By Technical Paper Link - 26 Feb, 2023 - Comments: 0

A new technical paper titled "CompaSeC: A Compiler-Assisted Security Countermeasure to Address Instruction Skip Fault Attacks on RISC-V" was published by researchers at TU Munich and Fraunhofer Institute for Applied and Integrated Security (AISEC). Abstract "Fault-injection attacks are a risk for any computing system executing security-relevant tasks, such as a secure boot process. While ha... » read more

Chip Industry’s Technical Paper Roundup: Jan. 31
By Linda Christensen - 31 Jan, 2023 - Comments: 0

New technical papers added to Semiconductor Engineering’s library. [table id=77 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us posting l... » read more

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