tag: UC Berkeley

Characteristics and Potential HW Architectures for Neuro-Symbolic AI
By Technical Paper Link - 23 Sep, 2024 - Comments: 0

A new technical paper titled "Towards Efficient Neuro-Symbolic AI: From Workload Characterization to Hardware Architecture" was published by researchers at Georgia Tech, UC Berkeley, and IBM Research. Abstract: "The remarkable advancements in artificial intelligence (AI), primarily driven by deep neural networks, are facing challenges surrounding unsustainable computational trajectories, li... » read more

Chip Industry Technical Paper Roundup: Sept. 3
By Linda Christensen - 03 Sep, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=256 /] More ReadingTechnical Paper Library home » read more

GPU Microarchitecture Integrating Dedicated Matrix Units At The Cluster Level (UC Berkeley)
By Technical Paper Link - 27 Aug, 2024 - Comments: 0

A new technical paper titled "Virgo: Cluster-level Matrix Unit Integration in GPUs for Scalability and Energy Efficiency" was published by UC Berkeley. Abstract "Modern GPUs incorporate specialized matrix units such as Tensor Cores to accelerate GEMM operations central to deep learning workloads. However, existing matrix unit designs are tightly coupled to the SIMT core, limiting the size a... » read more

Security Technical Paper Roundup: Aug. 27
By Liz Allan - 27 Aug, 2024 - Comments: 0

A number of hardware security-related technical papers were presented at the August 2024 USENIX Security Symposium. The organization provides open access research, and the presentation slides and papers are free to the public. Topics include side-channel attacks and defenses, embedded security, fuzzing, fault injection, logic locking, Rowhammer, and more. Here are some highlights with associate... » read more

Chip Industry Technical Paper Roundup: July 30
By Linda Christensen - 30 Jul, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library, including a best paper award winner at ISCA. [table id=246 /] More ReadingTechnical Paper Library home » read more

Using Diffusion Models to Generate Chip Placements (UC Berkeley)
By Technical Paper Link - 27 Jul, 2024 - Comments: 0

A technical paper titled “Chip Placement with Diffusion” was published by researchers at UC Berkeley. Abstract: "Macro placement is a vital step in digital circuit design that defines the physical location of large collections of components, known as macros, on a 2-dimensional chip. The physical layout obtained during placement determines key performance metrics of the chip, such as power... » read more

Will AI Disrupt EDA?
By Brian Bailey - 25 Jul, 2024 - Comments: 1

Generative AI has disrupted search, it is transforming the computing landscape, and now it's threatening to disrupt EDA. But despite the buzz and the broad pronouncements of radical changes ahead, it remains unclear where it will have impact and how deep any changes will be. EDA has two primary roles — automation and optimization. Many of the optimization problems are NP hard, which means ... » read more

Chip Industry Week In Review
By The SE Staff - 10 May, 2024 - Comments: 0

Synopsys refocused its security priorities around chips, striking a deal to sell off its Software Integrity Group subsidiary to private equity firms Clearlake Capital Group and Francisco Partners for about $2.1 billion. That deal comes on the heels of Synopsys' recent acquisition of Intrinsic ID, which develops physical unclonable function IP. Sassine Ghazi, Synopsys' president and CEO, said in... » read more

Chip Industry Technical Paper Roundup: April 2
By Linda Christensen - 02 Apr, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library. [table id=211 /] Find last week’s technical paper additions here. » read more

Designing AI Hardware To Deal With Increasingly Challenging Memory Wall (UC Berkeley)
By Technical Paper Link - 25 Mar, 2024 - Comments: 0

A new technical paper titled "AI and Memory Wall" was published by researchers at UC Berkeley, ICSI, and LBNL. Abstract "The availability of unprecedented unsupervised training data, along with neural scaling laws, has resulted in an unprecedented surge in model size and compute requirements for serving/training LLMs. However, the main performance bottleneck is increasingly shifting to memo... » read more

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