Analysis Of Multi-Chiplet Package Designs And Requirements For Production Test Simplification

By Vineet Pancholi - 21 Nov, 2024 - Comments: 0

In recent years there has been a sharp rise of multi-die system designs. Numerous publications targeting a large variety of applications exist in the public domain. One presentation [2] on the IEEE’s website does a good job of detailing the anecdotal path of multi-die systems by way of chiplet building blocks integrated within a single package [2]. The presentation includes references to a ha... » read more

Defining The Chiplet Socket

By Brian Bailey - 29 Aug, 2024 - Comments: 0

Experts At The Table: The semiconductor industry has been buzzing with the possibilities surrounding chiplets, but so far this packaging technology has been confined to large semiconductor companies that are vertically integrated. The industry has been attempting to open this up to a broader group of people. To work out what this means for chiplets, and what standardization will be required, Se... » read more

Chiplets: More Standards Needed

By Andy Heinig - 13 Apr, 2023 - Comments: 1

Recent months have seen new advances in chiplet standardization. For example, consortia such as Bunch of Wires (BoW) and Universal Chiplet Interconnect Express (UCIe) have made progress in developing standards for die-to-die (D2D) interfaces in a chiplet’s design. Far from being a new phenomenon in communication, these types of standards are established for all forms of wired and wireless com... » read more

Is UCIe Really Universal?

By Brian Bailey - 22 Nov, 2022 - Comments: 3

Chiplets are rapidly becoming the means to overcome the slowing of Moore's Law, but whether one interface is capable of joining them all together isn't clear yet. The Universal Chiplet Interconnect Express (UCIe) believes it will work, but some in the industry remain unconvinced. At least part of the problem is that interconnect standards are never truly finished. Even today, the protocols tha... » read more

How Memory Design Optimizes System Performance

By John Koon - 21 Sep, 2022 - Comments: 0

Exponential increases in data and demand for improved performance to process that data has spawned a variety of new approaches to processor design and packaging, but it also is driving big changes on the memory side. While the underlying technology still looks very familiar, the real shift is in the way those memories are connected to processing elements and various components within a syste... » read more

What Is UCIe?

By Manuel Mota - 13 Sep, 2022 - Comments: 0

The semiconductor industry is undertaking a major strategy shift towards multi-die systems. The shift is fueled by several converging trends: Size of monolithic SoCs is becoming too big for manufacturability Some SoC functionalities may require different process nodes for optimal implementation Desire for enhanced product scalability and composability is increasing Multi-die syste... » read more

Standardizing Chiplet Interconnects

By John Koon - 23 May, 2022 - Comments: 0

The chip industry is making progress on standardizing the infrastructure for chiplets, setting the stage for faster and more predictable integration of different functions and features from different vendors. The ability to choose from a menu of small, highly specialized chips, and to mix and match them for specific applications and use cases, has been on the horizon for more than a decade. ... » read more

Chiplets: Current Status

By Andy Heinig - 12 May, 2022 - Comments: 0

Recent weeks have seen a number of interesting developments in the area of chiplets. An increasing number of products based on chiplets have been brought to market, especially in the processors segment. For example, Apple and AMD now have processors with chiplets on the market and under production in high volumes. On one hand, this means that sufficient production capacity has now been built up... » read more

UCIe: Marketing Ruins It Again

By Brian Bailey - 24 Mar, 2022 - Comments: 1

You may have seen the press release and articles recently about a new standard called UCIe. It stands for Universal Chiplet Interconnect Express. The standard is a great idea and will certainly help the market for chiplet-based designs to advance. But the name — Argggh. More on that later. First, let's talk about what it is. You may notice the name looks similar to PCIe (Peripheral Compone... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?