Chiplets: More Standards Needed

Current chiplet interface standardization efforts fall short when it comes to handling analog signals and power.


Recent months have seen new advances in chiplet standardization. For example, consortia such as Bunch of Wires (BoW) and Universal Chiplet Interconnect Express (UCIe) have made progress in developing standards for die-to-die (D2D) interfaces in a chiplet’s design. Far from being a new phenomenon in communication, these types of standards are established for all forms of wired and wireless communication. Such standards always consist of various layers, or levels. In many cases, standardization starts at a very low level with a specification of the electrical signals. This physical layer encompasses the voltage level as well as the frequencies with which signals are transmitted. In the BoW and UCIe standards referred to above, all the signals are standardized at the electrical level and are therefore interoperable. In many cases, further levels of standards are then layered on top to perform functions such as identifying and correcting errors. Other standards at still higher levels enable data to be organized into packages, which can again be uniquely assigned once they reach the recipient. In its current form, the UCIe standard already specifies and standardizes such additional protocol layers built upon electrical signaling standards. The BoW consortium has also taken the first steps in this direction.

However, the current version of the standard only specifies the interface between the various chiplets. Moreover, the protocols are currently designed in a way that makes them suitable only for applications that function exclusively using digital signals. In applications that require the transmission of analog signals, there is currently no standardization at all when it comes to the interface between chiplets. Even if steps are taken to digitize this analog data beforehand, it is often only the raw data that ends up being transferred between chiplets. Yet this situation is covered only to a limited extent by the current UCIe standards. Analog data is often digitized with a specific bit width. This is based on the signal and application and, in many cases, is not a multiple of 8 bits. Current standards, however, work on the basis of multiples of 8 bits. Obviously, bit padding can be used to make the data in the protocols conform to the standard, yet such space-filling bits do not contain any information, which means that a large portion of the data transfer rate is wasted. By implication, then, further standards must be created for applications in the field of heterogeneous integration, or existing standards must be extended to cover these kinds of specifically analog interfaces.

The current version of the UCIe standard is designed to have one processor in the chiplet, the capabilities of which are extended by additional accelerators on other circuits of the chiplet. However, system architectures in heterogeneous systems (e.g. for autonomous driving) will be designed in a substantially different way, namely with distributed multi-processor systems, each on different circuits of the chiplet. This necessitates the development of new system concepts, which must themselves be standardized to facilitate interoperability. Since these concepts are yet to be developed, however, this poses a significant challenge. It is therefore too early to develop standards in this area.

Supplying chiplets with power is another important issue. To genuinely achieve interoperability between chiplets built using different circuits from available chiplet building blocks, it is also necessary to specify and standardize the power supply. This calls for standardization of aspects such as voltage level and the sequence in which chiplet subcomponents are activated. It also requires the creation and standardization of interfaces. Other areas in which standards could be useful in the future include mechanical assemblies, testing, commissioning, and heat dissipation. An initial push toward standardization has already been made in several of these areas, and it is important that these efforts continue.


Erik Jan Marinissen (imec) says:

IEEE Std 1838™-2019 is the standard for 3D-DfT and is very applicable for chiplet-based designs. Released in early 2020, this new standard is now being supported by all three major EDA suppliers. IMEC has made a test chip and ARM has reported on early application of the new standard.

IEEE-SA has recently started a new Study Group, that is currently formulating a PAR (=Project Authorization Request) to start a standard development working group into test and repair of 3D inter-die interconnects. This is a.o. driven by Intel; with their Ponte Vecchio, they have a product out in the market that has more than 75,000 of such inter-die interconnects, which makes effective and efficient testing and repair an economic necessity.

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